Semiconductor Memory Spacer Layer Etching Process
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Solution Overview
Problem
The existing manufacturing methods for semiconductor memory devices face challenges with excessive etchant consumption, longer etching times, and poor side etching uniformity when using a single wet etching process to remove the spacer layer.
Innovation Solution
A dual etching process is employed, where a first anisotropic etching process is followed by a second isotropic etching process, using different etching techniques and etchants to efficiently remove the spacer layer on the memory cell region, with the first process stopping at a dielectric layer and the second process using a wet etching method to further remove the remaining spacer layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If a single wet etching process is used to remove the spacer layer, then the spacer layer can be removed, but excessive etchant consumption occurs
Solution Approach 1:
The single wet etching process is divided into two sequential etching processes: a first anisotropic etching process followed by a second isotropic wet etching process. This segmentation allows the removal of the spacer layer to be accomplished in stages, with the first process removing the majority of the spacer layer material and the second process completing the removal, thereby reducing overall etchant consumption while maintaining etching efficiency
Solution Approach 2:
The invention changes the etching parameters by switching from a single wet etching method to a combination of anisotropic and isotropic etching methods with different etchants. The first anisotropic etching process uses parameters optimized for directional removal, while the second wet etching process uses parameters optimized for complete removal, thereby improving both etchant efficiency and overall productivity
2Loss of time
If a single wet etching process is used to remove the spacer layer, then the spacer layer can be removed, but the etching time becomes longer
Solution Approach 1:
The etching process is segmented into two distinct stages: a first anisotropic etching process that rapidly removes the bulk of the spacer layer material, followed by a second wet etching process that completes the removal. This segmentation optimizes the total etching time by using the most efficient method for each stage, thereby reducing overall processing time and improving manufacturing efficiency
Solution Approach 2:
The two etching processes are performed in continuous sequence without interruption, maintaining the useful action of spacer layer removal throughout. The first anisotropic etching process continuously removes material in the desired direction, and the second wet etching process immediately follows to complete the removal, ensuring continuous productive action and minimizing total etching time
3Manufacturing precision
If a single wet etching process is used to remove the spacer layer, then the spacer layer can be removed, but the side etching uniformity deteriorates
Solution Approach 1:
The etching process is segmented into a first anisotropic etching process that provides excellent side etching uniformity through directional removal, followed by a second wet etching process that completes the removal with controlled isotropic action. This segmentation allows each process to contribute its strengths to achieving uniform side etching while maintaining overall process efficiency
Solution Approach 2:
The invention applies different etching qualities locally to different stages of the spacer layer removal process. The first anisotropic etching process provides highly directional, uniform side etching quality, while the second wet etching process provides complementary isotropic removal quality. This local quality differentiation ensures superior side etching uniformity throughout the entire spacer layer removal process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces etchant consumption and etching time while improving side etching uniformity, enhancing manufacturing efficiency and yield.
Implementation Method 1
A first etching process is performed to the spacer layer for removing a part of the spacer layer on the memory cell region
Implementation Method 2
A second etching process is performed after the first etching process for removing the spacer layer remaining on the memory cell region
Data Source
AI summary
A manufacturing method of a semiconductor memory device includes the following steps. A semiconductor substrate having a memory cell region and a peripheral region defined thereon is provided. Bit line structures are formed on the memory cell region. At least one gate structure is formed on the peripheral region. A spacer layer is formed covering the semiconductor substrate, the gate structure, and the bit line structures. The spacer layer is partly disposed on the memory cell region and partly disposed on the peripheral region. A first etching process is performed to the spacer layer for removing a part of the spacer layer on the memory cell region. At least a part of the spacer layer remains on the memory cell region after the first etching process. A second etching process is performed after the first etching process for removing the spacer layer remaining on the memory cell region.