Non-volatile Memory Spacers Suppress Secondary Electron Interference
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Solution Overview
Problem
As the size of EEPROMs decreases, the interference effect of secondary electrons on adjacent memory cells becomes more significant, leading to punch-through and short channel effects during programming operations, which are not effectively addressed by existing technologies.
Innovation Solution
A non-volatile memory design featuring a stacked gate structure with spacers between doped regions and the substrate, where the spacers are positioned to prevent punch-through and short channel effects by extending the path for secondary electrons and draining them, thereby suppressing interference during programming operations. The structure includes a substrate, a stacked gate structure with dielectric and conductive layers, and doped regions, with spacers made of dielectric materials to prevent electron interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the size of EEPROM is decreased to increase integration density, then manufacturing precision and device complexity are improved, but secondary electron interference on adjacent memory cells is aggravated
Solution Approach 1:
The memory cell structure is segmented into multiple functional layers including charge trapping layer, tunnel insulator, block insulator, and contact hole structures. This segmentation allows independent optimization of each layer to address secondary electron interference while maintaining small cell size
Solution Approach 2:
Different regions of the memory cell are given different properties: the charge trapping layer is positioned to capture secondary electrons, the block insulator prevents electron tunneling to adjacent cells, and contact holes are strategically placed to drain electrons. This local differentiation solves the interference problem without increasing overall cell size
2Reliability
If doped regions are deepened to suppress punch-through effect, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
A block insulator layer is introduced as an intermediary between the doped regions and the charge storage layer. This intermediary prevents direct electron tunneling (punch-through) while allowing the doped regions to maintain their depth for reliable charge injection, thus improving reliability without excessive manufacturing complexity
Solution Approach 2:
The solution moves from purely vertical depth control to a multi-dimensional approach by introducing lateral insulation structures (block insulator and contact holes). This dimensional transition allows deep doped regions to be formed without directly causing punch-through, as the electron path is blocked in another spatial dimension
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design effectively suppresses punch-through and short channel effects, preventing secondary electron interference during programming by deepening doped regions and ensuring no dielectric material blocks the electron path, thus enhancing memory cell programming efficiency.
Implementation Method 1
the charge storage layer is, for example, a charge trapping layer or a floating gate layer
Implementation Method 2
the charge storage layer is, for example, a charge trapping layer or a floating gate layer
Implementation Method 3
the spacers are positioned to prevent punch-through and short channel effects by extending the path for secondary electrons and draining them
Data Source
AI summary
A non-volatile memory including a substrate, a stacked gate structure, two doped regions and a plurality of spacers is provided. The stacked gate structure is disposed on the substrate, wherein the stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer and a conductive layer in sequence from bottom to top relative to the substrate. The doped regions are disposed in the substrate at two sides of the stacked gate structure, respectively, and bottom portions of the doped regions contact with the substrate under the doped regions. The spacers are respectively disposed between each side of each of the doped regions and the substrate, and top portions of the spacers are lower than top portions of the doped regions.