Non-Volatile Memory Charge Storage Spacers for Second Bit Effect
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Solution Overview
Problem
Non-volatile memory technologies face challenges with the second bit effect and program disturbance, particularly as memory size decreases, affecting operation windows and device performance due to reduced channel lengths and increased proximity of memory cells.
Innovation Solution
A manufacturing method for non-volatile memory involving the formation of a first oxide layer with protrusions, doped regions, and charge storage spacers on the sidewalls, where the charge storage spacers are formed using nitride, polysilicon, or high-k materials, and are designed to confine charges effectively, preventing the second bit effect and program disturbance by controlling spacer thickness and structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory size is reduced to increase storage density, then storage capacity is improved, but second bit effect becomes more severe
Solution Approach 1:
The charge storage function is segmented into two independent parts: the charge trapping structure (nitride layer) and the charge storage spacers formed on its sidewalls. This segmentation isolates the charge storage regions, preventing interference between adjacent bits and eliminating the second bit effect while maintaining high storage density.
Solution Approach 2:
Charge storage spacers act as intermediary structures between the charge trapping structure and the surrounding environment. These spacers confine charges locally on the sidewalls, serving as a mediator that prevents charge interference between adjacent memory cells while enabling continued miniaturization.
2Productivity
If channel length is reduced to increase storage density, then storage capacity is improved, but second bit effect becomes more severe
Solution Approach 1:
The invention transitions from planar charge storage to three-dimensional charge storage by forming charge storage spacers on the sidewalls of the charge trapping structure. This dimensional change allows independent control of charge storage regions, maintaining operation window quality even as channel length is reduced for higher density.
3Quantity of substance
If distance between memory cells is reduced to increase storage density, then storage capacity is improved, but program disturbance increases
Solution Approach 1:
The charge storage spacers provide localized charge confinement with specific material properties (nitride, polysilicon, or high-k dielectric) tailored for each storage region. This local quality control ensures that charges are confined precisely where needed, preventing program disturbance to adjacent cells even when they are closely spaced.
Data Source
AI summary
A non-volatile memory and a manufacturing method thereof are provided. In this method, a first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the pair of charge storage spacers. A conductive layer is formed on the second oxide layer, wherein the conductive layer is located completely on the top of the pair of charge storage spacers.