Variable Resistance Memory Spacers for Electrical Variation Control
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Solution Overview
Problem
The challenge in developing highly-integrated semiconductor devices is the need to reduce variations in electrical characteristics of cross-point stack memory devices to enhance reliability, particularly as these devices are downscaled, leading to increased variations in set and reset resistances and reduced sensing margins.
Innovation Solution
A memory device is designed with a 3D cross-point stack structure, featuring electrode line layers and memory cell layers with spacers of varying thicknesses to control electrical characteristics, where the spacers exert compressive or tensile stress on variable resistance patterns, and the thickness of these spacers is adjusted to minimize variations in set and reset resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dimension of each layer in the cross-point stack memory device is reduced to achieve high-density data storage, then the integration density is improved, but the variations in electrical characteristics of the memory cells increase
Solution Approach 1:
The patent applies local quality by forming spacers with different thicknesses at different locations within the memory device. Specifically, first spacers are formed with a first thickness and second spacers are formed with a second thickness that is different from the first thickness. This local variation in spacer thickness allows for compensation of electrical characteristic variations in memory cells while maintaining high integration density through the scaled-down layer dimensions.
2Length of moving object
If the dimension of each layer is reduced to downscale the device, then the device size is improved, but the sensing margin is reduced
Solution Approach 1:
The patent employs parameter changes by varying the thickness parameter of spacers at different locations. The first spacers have a first thickness and the second spacers have a second thickness, creating deliberate parameter variations that compensate for the reduced sensing margin caused by device downsaling. This allows the device to maintain adequate sensing margin despite the reduced overall dimensions.
3Length of moving object
If the dimension of each layer is reduced to downscale the device, then the device size is improved, but the variations in set and reset resistances increase
Solution Approach 1:
The patent addresses resistance variations through local quality by forming spacers with different thicknesses at different locations. The first spacers with a first thickness and second spacers with a second thickness create localized electrical characteristic adjustments that compensate for resistance variations in memory cells, thereby improving manufacturing precision despite device downsaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces variations in electrical characteristics and enhances the sensing margin, leading to improved reliability and performance of the memory device by controlling the set and reset resistances, thereby maximizing the integration density and reliability of the 3D cross-point stack structure.
Implementation Method 1
at least one of the plurality of first spacers and the plurality of second spacers may include a material exerting a compressive or tensile stress on the variable resistance patterns
Data Source
AI summary
The inventive concept provides a memory device, in which memory cells are arranged to have a low variation in electrical characteristics and thereby enhanced reliability, an electronic apparatus including the memory device, and a method of manufacturing the memory device. In the memory device, memory cells at different levels may be covered with spacers having different thicknesses, and this may control resistance characteristics (e.g., set resistance) of the memory cells and to reduce a vertical variation in electrical characteristics of the memory cells. Furthermore, by adjusting the thicknesses of the spacers, a sensing margin of the memory cells may increase.