Memory Device Spare Cell Mapping for Defect Isolation

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Solution Overview

Problem

Semiconductor memory devices face reliability and lifespan issues due to defective memory cells, which existing error correction codes cannot fully address, leading to unserviceable memory segments and device failure.

Innovation Solution

A method that differentiates memory cells with data errors in real-time and replaces them with spare cells, while backing up address information into non-volatile memory to prevent reassociation and enhance operational speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction codes are used to handle defective memory cells, then data integrity is improved, but memory segments become unserviceable when multiple errors occur and device lifespan is reduced

Engineering Contradiction:
Improvedata integrityVSAvoiddevice lifespan
Core Design Contradiction:
ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The memory device is segmented into operational memory cells and spare memory cells. When data errors occur in specific memory cells, those cells are identified and isolated, and the affected memory segment is replaced by mapping to spare memory cells through a replacement register, allowing the defective segment to be excluded from future operations

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Spare memory cells are pre-configured and reserved before defects occur. The replacement register is pre-established with mapping relationships between defective address information and spare memory cell addresses, enabling immediate redirection of operations away from defective cells without waiting for error detection and correction processes

Inventive Principle:
Principle #10Preliminary action

2Reliability

If memory cells with data errors are replaced by spare memory cells in real-time, then reliability is improved, but device complexity increases due to additional management mechanisms

Engineering Contradiction:
Improvememory operation reliabilityVSAvoidaddress management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A replacement register acts as an intermediary component between the address generation unit and the memory cell array. This register stores mapping relationships between defective address information and spare memory cell addresses, intercepting and redirecting address accesses before they reach the defective memory cells, thereby managing complexity in a centralized location rather than dispersing it throughout the memory access path

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The address mapping system is dynamic and adaptive. The replacement register can be updated with new mapping relationships as defects are discovered, and the system dynamically redirects address accesses based on the current state of defective cells. This dynamic approach allows the system to adapt to evolving defect patterns without requiring complete reconfiguration of the memory architecture

Inventive Principle:
Principle #15Dynamics

3Reliability

If address information is backed up into non-volatile memory, then reliability is improved by preventing reassociation with defective cells, but manufacturing complexity increases

Engineering Contradiction:
Improveaddress information persistenceVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The address information representing defective memory cell locations is copied and stored in a non-volatile memory cell. This creates a persistent backup of the defect map that survives power cycles and reset operations. The backup copy is used to prevent reassociation with defective cells after device restart, ensuring that the defect information is retained across different operational states

Inventive Principle:
Principle #26Copying

Data Source

PatentEP3964941B1Read-write method and memory device
Publication Date: 2024.02.28 CHANGXIN MEMORY TECH INC
  • EP3964941B1 patent drawingFigure 1
  • EP3964941B1 patent drawingFigure 2
  • EP3964941B1 patent drawingFigure 3

AI summary

A method for reading and writing and a memory device are provided. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, where the preset memory space is provided with a plurality of memory bits, each of the plurality of memory bits being associated with a respective spare memory cell; and backing up the address information stored in the preset memory space into a non-volatile memory cell according to a preset rule. Address information corresponding to an invalid memory cell is differentiated, in real time, from address information corresponding to a valid memory cell, and the invalid memory cell is replaced by the spare memory cell, thereby greatly improving the reliability of the memory device and prolonging the lifespan of the memory device. In addition, the address information stored in the preset memory space is backed up into a non-volatile memory cell according to a preset rule, thereby greatly increasing a running speed of the memory device.