In-Memory Parallel Spike Processing for Scalable Spiking Neural Networks
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Solution Overview
Problem
Scalable implementation of spiking neural networks (SNNs) is challenging due to the significant computing resources required for processing spikes, especially when simulating the large number of neurons and synapses present in biological neural networks (BNNs, such as those found in human brains.
Innovation Solution
A scalable SNN architecture is implemented using special-purpose memory devices configured as nodes, which perform in-memory processing (PIM) and utilize SIMD or MIMD pipelines for spike delivery, synaptic integration, and neuronal dynamics, incorporating memory arrays and controllers to efficiently manage synaptic connections and neuron communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional processing architectures are used to simulate spikes in SNNs, then computing resource demands increase significantly, but processing speed and scalability deteriorate
Solution Approach 1:
The patent replaces conventional von Neumann architecture with in-memory computing architecture where spike processing operations are performed directly within the memory array. This substitution eliminates the mechanical data movement between separate processing and memory units, achieving both high processing speed and low energy consumption by keeping computations at the data location.
Solution Approach 2:
The patent implements parallel processing across multiple memory banks and uses three-dimensional memory structures to handle large-scale SNN simulations. This dimensional expansion allows simultaneous processing of multiple spikes and neurons, dramatically increasing productivity while maintaining energy efficiency through spatial parallelism.
2Measurement precision
If the number of neurons and synapses is increased to match biological neural networks, then simulation accuracy improves, but device complexity and computing resource requirements worsen
Solution Approach 1:
The patent divides the large-scale neural network into multiple manageable memory banks, each handling a subset of neurons and synapses. This segmentation allows accurate simulation of billions of connections while keeping individual processing units simple and scalable, reducing overall device complexity through modular architecture.
Solution Approach 2:
The patent implements a universal in-memory processing unit that can handle various neural network operations (spike delivery, synaptic integration, neuronal dynamics) using the same hardware structure. This multi-functionality enables accurate simulation of complex BNNs without requiring specialized complex circuits for each operation.
3Productivity
If conventional memory architectures are used, then data storage capacity is sufficient, but processing speed and energy efficiency for spike delivery and synaptic integration deteriorate
Solution Approach 1:
The patent merges memory storage and processing functions into a unified in-memory computing architecture. Spike delivery and synaptic integration operations are performed directly within the memory array where data is stored, eliminating energy-consuming data movement and achieving high throughput with low energy consumption.
Solution Approach 2:
The patent introduces specialized in-memory processing units as intermediaries between the memory array and external controllers. These intermediaries handle spike delivery and synaptic integration operations locally within the memory structure, reducing the energy burden on the main memory system while maintaining high processing throughput.
Data Source
AI summary
The disclosed embodiments are related to storing critical data in a memory device such as Flash or DRAM memory device. In one embodiment, a device comprising a plurality of parallel processors is disclosed, the plurality of parallel processors configured to: perform a search and match operation, the search and match operation loading a plurality of synaptic identifier bit strings and a plurality of spike identifier bit strings, the search and match operation further generating a plurality of bitmasks; perform a synaptic integration phase, the synaptic integration phase generating a plurality of synaptic current vectors based on the plurality of bitmasks, the synaptic current vectors associated with respective synthetic neurons; solve a neural membrane equation for each of the synthetic neurons; and update membrane potentials associated with the synthetic neurons, the membrane potentials stored in a memory device.