Memory Splitter Chip Expands GPU DRAM Capacity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional graphics processing systems have limited DRAM memory space due to the fixed pin layout of the external memory interface, which restricts the number of DRAM units that can be connected to the graphics processing unit (GPU), affecting overall performance and being costly to modify.
Innovation Solution
A memory splitter chip manages data transmission between a parallel processing subsystem and multiple external memory devices, determining optimal transmission frequencies to couple multiple DRAM units to the GPU, thereby expanding memory capacity and improving performance without modifying the GPU interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the external memory interface is modified to include more pins so that more DRAM units can be connected, then the DRAM memory space available to the GPU is increased, but the circuitry of the external memory interface becomes more complex and manufacturing cost significantly increases
Solution Approach 1:
A memory splitter chip is introduced as an intermediary device between the GPU and multiple DRAM units. The memory splitter chip receives commands from the GPU via the existing external memory interface and distributes them to appropriate DRAM units, enabling expanded memory capacity without modifying the GPU interface circuitry.
2Quantity of substance
If the external memory interface is modified to include more pins so that more DRAM units can be connected, then the DRAM memory space available to the GPU is increased, but the design becomes rigid and cannot adapt to different DRAM memory space requirements
Solution Approach 1:
The memory splitter chip provides dynamic adaptability by allowing the system to connect different numbers and types of DRAM units based on memory requirements. The chip dynamically manages command distribution and data transmission to multiple DRAM units, enabling flexible configuration without fixed interface constraints.
3Quantity of substance
If multiple DRAM units are connected directly to the GPU via the external memory interface, then the memory capacity is increased, but the data transmission management becomes complex due to frequency synchronization requirements
Solution Approach 1:
The memory splitter chip implements feedback mechanisms to manage data transmission between the GPU and multiple DRAM units. It monitors transmission frequencies, manages command distribution, and coordinates data flow to maintain synchronization across multiple memory devices without requiring complex modifications to the GPU interface.
Data Source
AI summary
The memory splitter chip couples multiple DRAM units to the PPU, thereby expanding the memory capacity available to the PPU for storing data and increasing the overall performance of the graphics processing system. The memory splitter chip includes logic for managing the transmission of data between the PPU and the DRAM units when the transmission frequencies and the burst lengths of the PPU interface and the DRAM interfaces differ. Specifically, the memory splitter chip implements an overlapping transmission mode, a pairing transmission mode or a combination of the two modes when the transmission frequencies or the burst lengths differ.