Semiconductor Memory SPO Operation Segmentation

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Solution Overview

Problem

Existing semiconductor memory devices face challenges in maintaining stability during sudden power off (SPO) events, leading to potential data loss and increased power consumption, as existing solutions either interrupt essential operations or fail to manage non-essential operations correctly.

Innovation Solution

A semiconductor memory device and controller system that includes a control logic to identify and interrupt non-essential operations during an SPO, using a SPO process command to differentiate between protection and general operations, ensuring that only non-essential operations are halted while maintaining essential operations like SLC programming.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If all operations are interrupted during sudden power off, then power consumption is reduced, but essential operations like SLC programming may be lost

Engineering Contradiction:
Improvepower consumptionVSAvoiddata loss
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent segments operations into two categories: protection operations (SLC programming) and general operations (MLC/TLC/QLC programming, read, erase). This segmentation allows selective interruption during SPO events, where only general operations are halted while protection operations continue, thereby reducing power consumption without causing data loss in critical operations.

Inventive Principle:
Principle #1Segmentation

2Stability of the object's composition

If all operations are interrupted during sudden power off, then stability is improved, but non-essential operations cannot be properly managed

Engineering Contradiction:
Improvesystem stabilityVSAvoidoperation management flexibility
Core Design Contradiction:
Stability of the object's compositionVSAdaptability or versatility

Solution Approach 1:

The patent divides operations into protection operations and general operations, enabling differentiated management during SPO events. This segmentation provides both stability (by interrupting non-essential operations) and adaptability (by allowing essential operations to continue), resolving the contradiction between system stability and operation management flexibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic operation management by selectively interrupting only general operations while allowing protection operations to continue during SPO events. This dynamic approach adjusts system behavior based on operation type, maintaining stability while preserving necessary operational flexibility.

Inventive Principle:
Principle #15Dynamics

3Loss of energy

If protection operations are interrupted, then power consumption is reduced, but data integrity is compromised

Engineering Contradiction:
Improvepower consumptionVSAvoiddata integrity
Core Design Contradiction:
Loss of energyVSLoss of information

Solution Approach 1:

The patent segments operations into protection operations (which maintain data integrity) and general operations (which can be interrupted). By selectively continuing protection operations during SPO events, the system reduces power consumption from non-essential operations while preserving data integrity through continued execution of critical protection operations.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11340802B2Semiconductor memory device, controller, memory system and method thereof
Publication Date: 2022.05.24 SK HYNIX INC
  • US11340802B2 patent drawing
  • US11340802B2 patent drawing
  • US11340802B2 patent drawing

AI summary

A memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a plurality of planes and performs a protection operation and a general operation on the plurality of planes. The controller controls an operation of the semiconductor memory device by transferring a Sudden Power Off (SPO) process command, which is generated in response to a Sudden Power Off (SPO) that occurs in the memory system, to the semiconductor memory device. The semiconductor memory device is configured to interrupt the general operations among operations performed on the plurality of planes in response to the SPO process command.