3D Memory Stack Air-Gap Insulation for Parasitic Capacitance Control
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Solution Overview
Problem
The operational reliability of three-dimensional semiconductor devices deteriorates as the number of stacked memory cells increases, leading to reduced performance and efficiency.
Innovation Solution
A semiconductor device with a stack structure featuring conductive patterns, a channel structure, and a slit insulating layer, where air gaps are defined between the conductive patterns, and the slit insulating layer is formed by oxidizing buffer patterns to minimize parasitic capacitance and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of stacked memory cells is increased to improve integration degree, then device complexity increases, but operational reliability deteriorates
Solution Approach 1:
The patent divides the stack structure into multiple segments by introducing air gaps between conductive patterns. These air gaps segment the continuous structure into isolated regions, reducing parasitic capacitance coupling between adjacent memory cells. This segmentation allows higher integration without proportionally increasing interference, thus maintaining operational reliability despite increased device complexity.
Solution Approach 2:
The patent applies different properties to different regions of the stack structure. Specifically, air gaps are introduced in specific locations between conductive patterns where parasitic capacitance would otherwise be high. This local modification of the structure's properties (adding air gaps in specific regions) reduces electromagnetic interference locally without affecting the overall integration density, thereby resolving the contradiction between high integration and reliable operation.
2Area of stationary object
If conductive patterns are placed closer together to increase integration, then area is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the harmful dielectric material between conductive patterns and replaces it with air gaps. By removing the solid dielectric that causes parasitic capacitance and substituting it with air (which has much lower permittivity), the patent maintains close spacing of conductive patterns for high integration while dramatically reducing parasitic capacitance. This extraction of the harmful element directly addresses the contradiction between small area and low parasitic capacitance.
Solution Approach 2:
The patent introduces air gaps that create a porous or hollow structure between conductive patterns. Instead of using solid dielectric material throughout, the structure incorporates void spaces (air gaps) that reduce the effective permittivity in the region between conductive patterns. This porous approach allows close spacing for high density while minimizing the capacitance-forming dielectric volume, resolving the area versus parasitic capacitance trade-off.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively minimizes parasitic capacitance and maintains operational reliability by forming relatively large air gaps between conductive patterns, thereby improving the performance and efficiency of three-dimensional semiconductor devices.
Implementation Method 1
forming a slit insulating layer sealing the air gaps. Forming the slit insulating layer includes oxidizing the buffer patterns
Data Source
AI summary
A semiconductor device includes a stack structure including conductive patterns spaced apart from each other, a channel structure penetrating the stack structure, and a slit insulating layer penetrating the stack structure. Air gaps are defined between the conductive patterns. The slit insulating layer includes a first interposition part covering a sidewall of one of the conductive patterns and a second interposition part covering one of the air gaps from the side. A smallest width of the second interposition part is smaller than a smallest width of the first interposition part.