Vertical Memory Stack Alignment Keys for Precise Overlay Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration and accurate overlay alignment during the fabrication of three-dimensional memory cell arrays, leading to issues such as cracking and arcing of alignment keys.
Innovation Solution
The fabrication method involves forming stepped alignment keys with recess portions that serve as alignment keys, allowing for precise etching and pillar structure alignment by using these keys as barriers, thereby preventing cracking and arcing, and enhancing overlay accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional alignment methods are used for three-dimensional memory cell arrays, then fabrication process can proceed, but overlay accuracy deteriorates and alignment keys crack or arc
Solution Approach 1:
The method performs preliminary etching to form recess portions in the alignment key region before forming the final alignment keys. This preliminary action creates a stepped structure that prevents cracking and arcing during subsequent processing, thereby improving both overlay accuracy and alignment key reliability
Solution Approach 2:
The alignment key structure is segmented into multiple levels with recess portions, creating a stepped configuration. This segmentation allows the alignment key to better withstand etching processes without cracking or arcing, while maintaining precise overlay alignment
2Quantity of substance
If three-dimensional memory cell arrays are formed to improve integration, then device capacity increases, but overlay alignment accuracy deteriorates
Solution Approach 1:
The invention introduces vertical dimensionality through stepped alignment keys with recess portions at different heights. This three-dimensional alignment key structure enables precise overlay alignment for multi-layer memory cell arrays by providing distinct alignment references at each vertical level
Solution Approach 2:
Preliminary etching creates recess portions that establish vertical reference levels before memory cell stack formation. This preliminary structuring enables accurate overlay alignment across multiple layers, supporting higher integration while maintaining precision
3Ease of manufacture
If etching is performed without stepped alignment keys, then process is simpler, but punch-through occurs and wafer defects increase
Solution Approach 1:
The stepped alignment key structure acts as an intermediary barrier during etching processes. The recess portions and stepped configuration serve as protective intermediaries that prevent punch-through while controlling etching progression, thereby reducing wafer defects without significantly complicating the manufacturing process
Data Source
AI summary
A method for fabricating a semiconductor device includes preparing a substrate including a first region and a second region, forming a lower alternating stack on the substrate; etching the lower alternating stack to form a lower opening in the second region, forming an upper alternating stack on the lower opening and the lower alternating stack to form recess portion caused by filling the lower opening in the second region, forming a mask layer on the upper alternating stack using the recess portion as an alignment key, and etching the upper alternating stack by using the mask layer as a barrier to form a pattern in the first region.