3D Memory Cell Stack With Integrated Bit Line Contacts
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges in reducing the volume of semiconductor devices while improving storage density and simplifying the fabrication process, particularly in memory systems like DRAM, where existing techniques either result in large volumes with low density or complex step structures.
Innovation Solution
A method involving a stack structure with interlayer insulating and composite material layers, where bit lines are integrated in the connection region, and contact structures extending from the stack structure to connect with bit lines, eliminating the need for step structures and simplifying the fabrication process by stacking memory cells in a second direction within the device region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional fabrication methods are used to maintain device functionality, then the device volume increases and storage density decreases, but if device volume is reduced for higher density, the fabrication process becomes more complex with step structures
Solution Approach 1:
The patent transitions from planar bit line arrangements to a three-dimensional stacked configuration where bit lines are positioned at different vertical levels within the stack structure. This dimensional change enables higher storage density by utilizing the vertical dimension while maintaining a simplified fabrication process through direct integration into the stack formation steps
2Quantity of substance
If step structures are introduced to accommodate bit lines in stacked memory cells, then storage density improves, but the fabrication process complexity increases significantly
Solution Approach 1:
The patent merges the bit line formation process with the stack structure fabrication by integrating bit lines directly into the composite material layers during stack formation. This consolidation eliminates the need for separate step structures and associated complex fabrication steps, achieving both high density and manufacturing simplicity
Data Source
AI summary
Examples of the present disclosure disclose a fabrication method of a semiconductor device, a semiconductor device and a memory system. The method includes: providing a stack structure including a device region and a connection region arranged in a first direction, the stack structure including an interlayer insulating layer and a composite material layer alternatively stacked in a second direction, the composite material layer including a bit line in the connection region, and the second direction intersecting the first direction; forming a contact hole in the connection region, the contact hole extending to the bit line from a first side of the stack structure in the second direction; and forming a contact structure connected with bit line in the contact hole.