3D Memory Stack Bonding with Gate Layers for Reliable Integration
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high integration density while maintaining reliability and reducing device volume, particularly in data storage applications where existing bonding methods do not adequately address the need for improved integration and reliability.
Innovation Solution
A semiconductor device structure is proposed, featuring a substrate with peripheral circuits, insulating structures, conductive patterns, and a stack structure with gate layers, including a barrier capping layer and passivation layer, which enhances integration and reliability by optimizing material layers and configurations to improve data storage capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If wafer bonding method is used to join structures, then degree of integration is improved, but device volume reduction and reliability maintenance become more difficult
Solution Approach 1:
The device is divided into two separate wafers (first wafer with peripheral circuit, second wafer with memory cell array) that are bonded together. This segmentation allows each wafer to be optimized independently for its specific function while achieving high integration through bonding, resolving the contradiction between integration improvement and reliability maintenance.
Solution Approach 2:
A pad structure with multiple layers (pad electrode, pad insulating layer, capping electrode, capping insulating layer) is introduced as an intermediary element between the two wafers. This pad structure facilitates reliable electrical connection and mechanical bonding between wafers, enabling high integration while maintaining connection reliability.
2Device complexity
If wafer bonding method is used to join structures, then degree of integration is improved, but device volume becomes larger
Solution Approach 1:
The device architecture transitions from planar integration to three-dimensional stacking, with the first wafer positioned below and the second wafer positioned above, connected through vertical pad structures. This dimensional change allows high integration density without proportionally increasing device footprint volume.
Data Source
AI summary
A device including a first structure and a second structure is provided. The device includes a substrate, a peripheral circuit and first junction pads on the substrate; a first insulating structure surrounding side surfaces of the first junction pads; second junction pads contacting the first junction pads; a second insulating structure on the first insulating structure; a passivation layer on the second insulating structure; an upper insulating structure between the passivation layer and the second insulating structure; a barrier capping layer between the upper insulating structure and the passivation layer; conductive patterns spaced apart from each other in the upper insulating structure; a first pattern structure between the upper insulating structure and the second insulating structure; a stack structure between the second insulating structure and the first pattern structure, and including gate layers; and a vertical structure passing through the stack structure and including a data storage structure and a channel layer.