Memory Die Stack Clock Sharing With Rank-Specific Wire Bonds
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Solution Overview
Problem
Existing semiconductor packages face challenges in optimizing wire bond connections for memory die stacks in LPDDR SDRAM, leading to potential short circuits and degradation of signal characteristics and performance over time.
Innovation Solution
Implementing a semiconductor package with a memory die stack that shares a clock signal between lower and upper bytes, utilizing separate die bond pads and optimized wire bonds for each rank to prevent overlapping and short circuits, thereby improving signal characteristics and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds are used to connect memory dies in a stack, then electrical connection is achieved, but short circuits and signal degradation occur over time
Solution Approach 1:
The patent divides the wire bond connections into separate groups for lower byte and upper byte ranks. Each rank has its own dedicated wire bonds connecting to corresponding die bond pads, preventing signal interference and short circuits between ranks over time.
Solution Approach 2:
The patent extracts the clock signal connection from shared resources and assigns dedicated wire bonds for each rank's clock signal. This separation eliminates the risk of short circuits between ranks and maintains signal integrity throughout the device's operational life.
2Device complexity
If clock signal is shared between lower and upper bytes, then device complexity is reduced, but short circuits may occur
Solution Approach 1:
The patent segments the clock signal distribution by creating separate die bond pads and wire bond paths for lower byte and upper byte ranks. Each rank receives its own dedicated clock signal connection, eliminating short circuit risks while maintaining relatively simple device architecture.
Solution Approach 2:
The patent applies local quality by providing rank-specific clock signal connections only where needed. Each memory die has die bond pads configured for its specific rank, ensuring reliable clock signal delivery without the complexity of fully differentiated routing throughout the entire device.
3Reliability
If separate die bond pads are used for each rank, then short circuits are prevented, but manufacturing complexity increases
Solution Approach 1:
The patent implements local quality by configuring die bond pads with specific functions at specific locations on each memory die. Each die has die bond pads designated for its rank's data and clock signals, preventing short circuits while maintaining manufacturability through localized rather than global differentiation.
Solution Approach 2:
The patent applies universality by using the same die bond pad structure and wiring methodology across all ranks. The multi-rank architecture uses consistent bonding techniques and pad configurations, making the manufacturing process relatively simple despite the increased reliability requirements.
Data Source
AI summary
A semiconductor package includes a memory die stack having a clock signal shared by lower and upper bytes. Each of a plurality of memory dies constituting the memory die stack of the semiconductor package includes a first clock circuit configured to generate a read clock signal for a lower byte and an upper byte constituting a data width of the memory die, and a plurality of first die bond pads corresponding to the number of ranks of a memory system including the memory die, and each of the plurality of first die bond pads is set for each rank. The first clock circuit is connected to, among the plurality of first die bond pads, a die bond pad corresponding to a rank to which the memory die belongs.