3D Memory Stack Contact Structure for Reliable Peripheral Connection
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Solution Overview
Problem
There is a need for high integration and large capacity nonvolatile semiconductor memory devices to support the increasing demand for portable electronic devices, with existing technologies facing challenges in enhancing operational reliability and structural efficiency.
Innovation Solution
A semiconductor memory device with a stack structure comprising alternately stacked insulating and conductive patterns, featuring a stepped structure and peripheral contact structures that electrically connect to peripheral transistors, along with a manufacturing method that forms these structures to improve connectivity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional contact structure is used to connect peripheral transistors to conductive patterns in the stack structure, then the connection is established, but the structural complexity increases and manufacturing difficulty arises
Solution Approach 1:
The contact structure is segmented into multiple distinct components: a contact hole penetrating the insulating layer, a contact electrode filling the contact hole, and a pad structure on top. This segmentation allows each component to be optimized independently for its specific function, simplifying the overall manufacturing process while ensuring reliable electrical connection between the peripheral transistor and conductive patterns
Solution Approach 2:
The contact electrode acts as an intermediary element between the peripheral transistor source/drain region and the pad structure. This intermediary component facilitates the electrical connection while providing a transition interface that simplifies the manufacturing process by separating the formation of the contact hole, contact electrode, and pad structure into distinct manufacturing steps
2Reliability
If the peripheral contact structure is positioned at lower levels, then it can connect to peripheral transistors, but connectivity to upper conductive patterns is limited
Solution Approach 1:
The contact structure extends in the vertical dimension by having the pad structure rise above the upper surface of the insulating layer. This dimensional extension allows the peripheral contact structure to establish electrical connection with conductive patterns located at upper levels of the stack structure, thereby improving electrical connectivity without requiring excessive lateral spacing
3Quantity of substance
If the stack structure is densely packed to increase integration, then capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The stack structure is segmented into alternating insulating layers and conductive patterns, with clearly defined interfaces between layers. This segmentation provides distinct manufacturing targets for each layer, allowing for better control of layer thickness, positioning, and alignment, thereby maintaining manufacturing precision even as integration density increases
Data Source
AI summary
A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.