3D Memory Stack Contact Layout for Smaller Peripheral Wafers
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Solution Overview
Problem
The dimension of the peripheral circuit wafer in three-dimensional memory systems limits the overall chip dimension, hindering further reduction and impacting storage density and integration, as high-voltage circuits cannot be further miniaturized.
Innovation Solution
Integrate low-voltage and ultra-low-voltage circuits on separate peripheral circuit wafers, with high-voltage circuits on another, using contact structures that penetrate through the stack structure to connect with gate conductor layers, allowing for multiple peripheral circuit wafers to be combined with memory array wafers without affecting performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high-voltage circuits are integrated on a peripheral circuit wafer, then the circuit functionality is complete, but the wafer dimension cannot be further reduced
Solution Approach 1:
The peripheral circuit wafer is segmented into multiple independent wafer units, each containing specific circuit blocks (high-voltage, low-voltage, ultra-low-voltage circuits). These segmented units can be independently designed and manufactured, then combined through wafer bonding to form the complete peripheral circuit functionality, thereby reducing the dimension of each individual wafer while maintaining complete circuit functionality.
Solution Approach 2:
The patent transitions from a single-plane wafer integration to a three-dimensional stacked architecture. Multiple peripheral circuit wafers are bonded together in the vertical dimension, allowing circuit functionality to be distributed across multiple layers. This dimensional transition enables complete circuit functionality while reducing the horizontal footprint of each wafer.
2Quantity of substance
If multiple peripheral circuit wafers are combined with memory array wafers, then storage density is improved, but the overall system complexity increases
Solution Approach 1:
Multiple peripheral circuit wafers and memory array wafers are merged together through wafer bonding to form an integrated three-dimensional memory structure. The peripheral circuit wafers are positioned at the edges of the memory array wafers, creating a unified system that achieves high storage density while managing complexity through systematic integration architecture.
Solution Approach 2:
The peripheral circuit wafers are designed with multi-functionality, containing different types of circuits (high-voltage, low-voltage, ultra-low-voltage) that can serve multiple functions within the memory system. This universal design reduces the need for separate dedicated wafers for each circuit type, thereby improving storage density while controlling system complexity.
3Reliability
If contact structures penetrate through the stack structure, then electrical connection is achieved, but manufacturing precision requirements increase
Solution Approach 1:
The contact structures are formed in advance during the wafer fabrication process, penetrating through the stack structure before the wafers are bonded together. This preliminary formation ensures that the contact structures are already in place and properly aligned within each wafer, reducing the alignment precision requirements during the subsequent wafer bonding process and improving manufacturing feasibility.
Data Source
AI summary
A semiconductor device includes a base and a stack structure. The base includes a first surface defining at least one memory plane region. The stack structure is disposed on the first surface, and includes a first portion located at the edge of the memory plane region and a second portion different from the first portion. The first portion includes first contact structures penetrating through the stack structure in a first direction and extending to the base. The second portion includes second contact structures electrically connected with corresponding gate conductor layers in the stack structure. A top surface of the first contact structure away from the base is flush with a top surface of the second contact structure away from the base.