3D Memory Stack Contact Structure for Lower-Cost High Density

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Solution Overview

Problem

The challenge of increasing storage density in semiconductor devices while simplifying the manufacturing process and reducing costs, particularly in three-dimensional memories, is hindered by complex processes and high material costs due to the increase in stacked layers.

Innovation Solution

A semiconductor device with a stacked structure comprising sub-stacked structures connected by a contact structure that extends along a direction, allowing independent operation of sub-stacked structures and reducing the need for word line contacts, thereby simplifying the manufacturing process and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of stacked layers is increased to increase storage density, then storage density is improved, but process complexity and manufacturing cost increase

Engineering Contradiction:
Improvestorage densityVSAvoidprocess complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The memory device is divided into multiple independent sub-stacked structures, each capable of independent operation. This segmentation allows complex high-density storage to be achieved through modular repetition of simpler units, reducing overall process complexity while maintaining high storage density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A single contact structure serves multiple functions by connecting to gate layers across multiple sub-stacked structures simultaneously. This multi-functional contact structure eliminates the need for separate word line contacts for each sub-stacked structure, simplifying the manufacturing process while supporting high storage density.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If the number of stacked layers is increased to increase storage density, then storage density is improved, but manufacturing cost increases

Engineering Contradiction:
Improvestorage densityVSAvoidmanufacturing cost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

Multiple sub-stacked structures are merged into a single integrated device with shared contact structures and peripheral circuits. This merging reduces the total number of discrete components and interconnections required, lowering manufacturing cost while achieving high storage density through the combined capacity of multiple sub-stacks.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The contact structure is designed to serve multiple sub-stacked structures simultaneously, reducing the number of contacts needed and simplifying the manufacturing process. This multi-functional approach directly reduces manufacturing cost while maintaining high storage density.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If word line contacts are formed for each sub-stacked structure, then connectivity is improved, but device complexity increases

Engineering Contradiction:
ImproveconnectivityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A single contact structure is designed to connect to gate layers in multiple sub-stacked structures simultaneously, providing the necessary connectivity for all sub-stacks through one unified structure. This eliminates the need for multiple separate word line contacts, reducing device complexity while maintaining reliable connectivity across all sub-stacked structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250386506A1Semiconductor device, manufacturing method thereof and memory system
Publication Date: 2025.12.18 YANGTZE MEMORY TECH CO LTD
  • US20250386506A1 patent drawing
  • US20250386506A1 patent drawing
  • US20250386506A1 patent drawing

AI summary

According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device may include a stacked structure including a plurality of sub-stacked structures stacked along a first direction. A sub-stacked structure of the plurality of sub-stacked structures may include select gate layers and gate layers stacked along the first direction. The semiconductor device may include a contact structure extending in the plurality of sub-stacked structures along the first direction and connected to the gate layers of the plurality of sub-stacked structures. At least one of the select gate layers may be connected to a peripheral circuit structure of the semiconductor device.