3D Memory Stack With Laterally Displaced Transistors
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Solution Overview
Problem
The challenge in semiconductor device design is to increase packing density and reduce fabrication costs while managing the complexity of electrical connections in three-dimensional memory arrays, where the number of decks and interconnect structures impede size reduction and storage density.
Innovation Solution
A semiconductor device with a stack structure comprising multiple decks, each with a thin film transistor control logic level, an access device level, and a memory element level, where the control logic level is in electrical communication with both the access device and memory element levels, and a base control logic structure, facilitating efficient operations through laterally displaced transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of decks in a 3D memory array is increased to improve storage density, then storage capacity is improved, but the complexity of routing and interconnect structures increases and sizing complications arise
Solution Approach 1:
The patent transitions from traditional 2D memory arrays to 3D stack structures with multiple decks stacked vertically. Each deck contains memory cells arranged in three dimensions, allowing storage density to increase by utilizing the vertical dimension rather than only expanding horizontally. This dimensional change enables higher storage capacity while managing interconnect complexity through vertical stacking architecture.
Solution Approach 2:
The patent implements a nested structure where multiple decks are stacked vertically, with each deck containing nested levels of memory cells, access devices, and control logic. The control logic devices are nested within the base control logic structure, and routing structures are nested to connect different decks. This nesting approach allows efficient space utilization and reduces the overall footprint while maintaining high storage density.
2Area of moving object
If the dimensions of individual features are reduced to increase packing density, then area utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the memory device into multiple discrete decks, each deck further segmented into distinct levels (memory cell level, access device level, control logic level). This segmentation allows each feature to be manufactured and optimized independently at appropriate dimensions, reducing the overall packing density requirements while maintaining manufacturability. The segmented architecture enables gradual scaling without requiring all features to be miniaturized simultaneously.
3Device complexity
If control logic devices are concentrated in a base control logic structure to simplify design, then design simplicity is improved, but the quantity and dimensions of routing structures increase creating sizing complications
Solution Approach 1:
The patent distributes control logic devices across multiple vertical levels and decks rather than concentrating them solely in a base structure. This vertical distribution shortens the lateral routing distances by allowing control logic to be positioned closer to the memory cells it controls in the three-dimensional space. The routing structures utilize vertical interconnects to connect different levels, reducing the overall routing length and complexity.
Data Source
AI summary
A semiconductor device comprises a stack structure comprising decks each comprising a memory element level comprising memory elements, and a control logic level in electrical communication with the memory element level and comprising control logic devices. At least one of the control logic devices of the control logic level of one or more of the decks comprises at least one device exhibiting transistors laterally displaced from one another. A memory device, a thin film transistor control logic assembly, an electronic system, and a method of operating a semiconductor device are also described.