3D Memory Stack Alignment Using a Staircase Dummy Mold
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and reducing process defects during fabrication.
Innovation Solution
A semiconductor device design featuring a substrate with a chip region and edge region, including a stack with a first staircase structure and a dummy mold structure with a second staircase structure, both aligned with alignment keys, to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally arranged to increase data storage capacity, then storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent creates a dummy mold structure that copies the staircase configuration of the actual memory stack in the scribe line region. This dummy structure serves as a reference copy that enables precise alignment verification through optical inspection, ensuring that the three-dimensionally arranged memory cells can be manufactured with high precision despite the complexity of vertical stacking.
Solution Approach 2:
The patent replaces mechanical alignment methods with optical field-based alignment. By creating a dummy mold structure with the same staircase pattern and using optical inspection systems to verify alignment between the dummy structure and alignment keys, the system achieves high manufacturing precision without relying on mechanical positioning methods.
2Manufacturing precision
If a dummy mold structure is formed in the scribe line region to improve alignment precision, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The dummy mold structure is formed only in the scribe line region, not across the entire substrate. This localized approach provides the necessary alignment reference where it is most needed (at the edges for dicing alignment) while minimizing the overall structural complexity and material usage compared to a full-coverage dummy structure.
Solution Approach 2:
The patent segments the substrate into chip regions and scribe line regions, and further segments the scribe line into regions with and without dummy mold structures. This segmentation allows the dummy mold structure to be strategically placed only where alignment verification is needed, reducing overall device complexity while maintaining manufacturing precision.
3Reliability
If the dummy mold structure is made to have substantially the same height as the stack, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent controls the height parameter of the dummy mold structure to be substantially equal to the height of the actual memory stack. This parameter matching ensures that optical inspection systems can accurately verify alignment between the dummy structure and alignment keys at all vertical levels, improving alignment reliability without requiring complex multi-step height adjustment processes.
Data Source
AI summary
A semiconductor device may include a substrate including a chip region and an edge region around the chip region, an alignment key disposed in the edge region of the substrate, a stack including conductive patterns and interlayer insulating layers, which are vertically and alternatingly stacked on the chip region of the substrate, the stack having a first staircase structure, and a dummy mold structure including dummy insulating layers and sacrificial patterns, which are vertically and alternatingly stacked on the edge region of the substrate, the dummy mold structure overlapping with the alignment key and having a second staircase structure. The dummy mold structure May have substantially the same height as the stack, when measured from the substrate.