3D Memory Stack Layout With Dummy Structures Against Warpage
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and ensuring reliability, particularly in three-dimensional memory cell structures.
Innovation Solution
The semiconductor device incorporates a memory cell region with a memory stack structure and a dummy structure, featuring interlayer insulating layers, gate electrodes, channel structures, and separation structures that enhance structural integrity and reliability by alternating stacking and directional separation of gate electrodes and dummy structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but structural stability deteriorates due to warpage during manufacturing and packaging
Solution Approach 1:
The patent introduces dummy stack structures that replicate the physical form and stacking configuration of actual memory stacks without containing functional memory cells. These dummy stacks are positioned adjacent to real stacks and undergo identical manufacturing processes, thereby experiencing the same thermal and mechanical stresses. This copying approach allows the dummy structures to absorb warpage and stress variations, protecting the functional memory stacks from deformation while maintaining the high-density three-dimensional architecture.
Solution Approach 2:
The dummy stack structures are designed with homogeneous material composition and geometric configuration matching the functional memory stacks. Both types of stacks use the same interlayer insulating layers, gate electrodes, and channel structures stacked in identical sequences. This homogeneity ensures that during manufacturing processes such as chemical mechanical polishing or thermal treatment, both dummy and functional stacks respond uniformly to external conditions, minimizing differential stress and warpage that would otherwise compromise structural stability.
2Reliability
If separation structures are added to improve structural stability, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory array into multiple blocks by introducing separation structures positioned between adjacent memory cell strings. These separation structures physically partition the continuous stack array into discrete segments, preventing stress propagation across the entire array and isolating potential failure points. The segmentation is achieved through insulating materials or etched regions that create mechanical and electrical isolation between neighboring stacks, thereby enhancing overall structural reliability without requiring complete redesign of the memory architecture.
Solution Approach 2:
The separation structures function as intermediary elements between functional memory stacks and dummy stack structures. Positioned at strategic locations, these intermediaries absorb and distribute mechanical stresses, thermal expansions, and manufacturing-induced warpage forces. By acting as buffer zones, the separation structures protect both functional and dummy stacks from direct stress exposure, reducing the complexity of stress management while maintaining structural integrity across the entire three-dimensional memory array.
Data Source
AI summary
A semiconductor device includes a memory cell structure on a substrate, and a dummy structure on a side of the memory cell structure. The memory cell structure includes a memory stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, channel structures penetrating through the memory stack structure and contacting the substrate, and first separation structures penetrating through the memory stack structure and extending in the first direction to separate the gate electrodes from each other in a second direction. The dummy structure includes dummy stack structures spaced apart from the memory stack structure and including first insulating layers and dummy gate electrodes alternately stacked, dummy channel structures penetrating through the dummy stack structures, and second separation structures penetrating through the dummy stack structures and extending in the second direction to separate the dummy gate electrodes from each other in the first direction.