Memory Stack Integration Using GAA Nanosheet Transistors
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently integrating resistance-based random access memory cells, such as MRAM, RRAM, PCRAM, and DRAM, due to limitations in fabrication processes that hinder the formation of advanced transistor structures like gate all around (GAA) transistors, which are crucial for next-generation memory devices.
Innovation Solution
The integration of gate all around (GAA) transistors is achieved through a method involving epitaxial growth and selective etching processes, forming nanosheet channels and replacing sacrificial layers with high-k/metal gate structures, enabling efficient fabrication of memory cells with improved conductivity and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional fabrication processes are used for integrating memory cells, then manufacturing simplicity is maintained, but the formation of advanced transistor structures like GAA transistors is hindered
Solution Approach 1:
The fabrication process is divided into distinct stages: forming sacrificial layers at specific positions, performing selective epitaxial growth in defined regions, and executing targeted removal steps. This segmentation enables complex GAA transistor structures to be built through manageable, sequential operations rather than attempting to form the complete structure in a single complex step.
Solution Approach 2:
Sacrificial layers are formed in advance at predetermined positions before the actual transistor structure construction. These preliminary sacrificial structures serve as templates that guide subsequent epitaxial growth and define the final transistor geometry. The preliminary action simplifies the overall process by establishing a framework before detailed structure formation begins.
2Manufacturing precision
If epitaxial growth and selective etching processes are used to form GAA transistors, then transistor structure advancement is achieved, but fabrication process complexity increases
Solution Approach 1:
Epitaxial growth is performed selectively in specific regions where transistor structures are required, rather than uniformly across the entire substrate. The growth conditions, rates, and durations are locally optimized for each region to achieve precise control over nanosheet formation, thickness, and crystal orientation. This local quality approach enables high precision in critical areas while maintaining efficiency elsewhere.
Solution Approach 2:
Sacrificial layers serve as intermediary structures that facilitate the formation of complex GAA transistor architectures. These temporary structures enable precise positioning and geometry definition during fabrication, then are removed after serving their guiding function. The intermediary approach allows complex structures to be built with greater ease by using removable templates rather than attempting direct formation.
3Reliability
If conventional memory cell integration is used, then fabrication simplicity is maintained, but conductivity and performance are limited
Solution Approach 1:
The GAA transistor structures incorporate multiple materials with complementary properties: semiconductor nanosheets for channel formation, high-k dielectric materials for gate insulation, and metal layers for gate electrodes and interconnects. This composite material approach enables superior electrical performance, higher conductivity, and improved reliability compared to conventional single-material structures, while the multi-material complexity is managed through the systematic fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the efficient fabrication of advanced transistor structures, enhancing the performance and scalability of resistance-based random access memory devices by improving conductivity and reducing fabrication complexities.
Implementation Method 1
The integration of gate all around (GAA) transistors is achieved through a method involving epitaxial growth and selective etching processes, forming nanosheet channels
Implementation Method 2
The integration of gate all around (GAA) transistors is achieved through a method involving epitaxial growth and selective etching processes
Data Source
AI summary
An integrated circuit (IC) device includes a front-side interconnect layer, a transistor device, a dielectric layer, a memory structure, and a backside interconnect layer. The transistor device has a gate structure over the front-side interconnect layer. The dielectric layer is over the transistor device. The memory structure is over the dielectric layer. The backside interconnect layer is over the memory structure.