3D Memory Stack Grooves for Multi-Depth Connection Region Formation
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Solution Overview
Problem
The existing manufacturing processes for three-dimensional semiconductor memory devices are complex and inefficient, particularly in forming connection regions, which hinders the integration and performance of these devices.
Innovation Solution
A semiconductor memory device structure comprising a substrate with a lower stack structure, an intermediate stack structure, and an upper stack structure, where grooves are etched to expose the lower stack structure at different depths, and steps are formed along the sidewalls of these grooves to facilitate the formation of connection regions, simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing manufacturing processes are used for three-dimensional semiconductor memory devices, then connection regions can be formed, but the manufacturing process becomes complex and inefficient with multiple mask processes and trimming steps
Solution Approach 1:
The stack structure is divided into multiple segments (lower stack structure, intermediate stack structure, upper stack structure) with grooves formed at different depths. This segmentation allows connection regions to be exposed at different levels, enabling simplified manufacturing by avoiding multiple mask processes while maintaining precise connection region formation.
Solution Approach 2:
The patent introduces vertical dimensionality by forming grooves at different depths (first depth, second depth, third depth) to expose connection regions. This multi-level vertical arrangement replaces complex planar mask processes with a more efficient depth-based exposure method, reducing manufacturing complexity while maintaining precision.
2Manufacturing precision
If multiple mask processes and trimming steps are used to form connection regions, then precise exposure is achieved, but manufacturing efficiency and productivity are reduced
Solution Approach 1:
The grooves are formed in advance at different depths before the final connection region formation step. This preliminary action of creating depth-varying grooves allows subsequent connection regions to be formed more efficiently without requiring multiple iterative mask and trim processes, thereby maintaining precision while improving productivity.
Solution Approach 2:
The manufacturing process is segmented into distinct depth levels with grooves formed at first, second, and third depths. This segmentation enables parallel or sequential formation of connection regions at different levels, reducing the total number of sequential mask and trim operations and thereby improving manufacturing efficiency while maintaining precise exposure.
3Ease of manufacture
If grooves are formed to expose lower stack structure at different depths, then manufacturing process is simplified, but structural complexity of the device increases
Solution Approach 1:
The patent manages structural complexity by organizing multiple stack structures and grooves in the vertical dimension rather than spreading complexity across the planar dimension. The lower, intermediate, and upper stack structures are arranged vertically with grooves at different depths, which simplifies the manufacturing process while containing structural complexity in a systematic three-dimensional arrangement.
Solution Approach 2:
The intermediate stack structure is positioned between the lower and upper stack structures, creating a nested vertical arrangement. The grooves at different depths expose portions of these nested structures in a hierarchical manner, which simplifies manufacturing by providing clear access paths while maintaining an organized, manageable structural complexity.
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.