3D Semiconductor Memory Stack Layout for Stable Hole Formation
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Solution Overview
Problem
Manufacturing semiconductor memory devices with a three-dimensional structure faces challenges in forming holes through stacked bodies as the number of stacks increases, making it difficult to enhance memory capacity per surface area effectively.
Innovation Solution
The semiconductor memory device design includes a first and second stacked body with an intermediate conductive and insulating layer, a semiconductor pillar with shifted parts, and a charge storage film containing nitrogen, hafnium, or aluminum, where the insulating film between the intermediate conductive layer and the semiconductor pillar reduces threshold voltage fluctuations and allows for efficient hole formation, enabling increased stack numbers and memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacks in the stacked body is increased to enhance memory capacity per surface area, then the memory capacity increases, but it becomes difficult to form holes by collective patterning
Solution Approach 1:
The patent divides the hole formation process into multiple stages. First, a preliminary pattern is formed to define initial hole positions. Then, additional stacks are formed around these preliminary patterns. Finally, the preliminary patterns are removed and new holes are formed in the remaining regions. This segmentation allows collective patterning to work effectively even with a large number of stacks by processing the structure in manageable portions rather than attempting to form all holes simultaneously.
2Quantity of substance
If the number of stacks is increased, then the memory capacity per surface area increases, but the threshold voltage fluctuations increase and electrical characteristics deteriorate
Solution Approach 1:
The patent introduces an intermediate conductive layer positioned between the lower and upper stacked bodies. This intermediate layer serves as a mediator that helps stabilize the electrical characteristics and reduce threshold voltage fluctuations. By providing this intermediate conductive structure, the patent enables the formation of more stacks while maintaining reliable electrical performance, thus resolving the contradiction between increasing memory capacity and maintaining electrical stability.
3Quantity of substance
If the number of stacks is increased, then the memory capacity per surface area increases, but the resistance increases and ON current decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional stacked structure with an intermediate conductive layer. By adding this intermediate dimension between the lower and upper stacks, the patent creates additional conductive pathways that reduce overall resistance. This dimensional change allows for increased stack density while maintaining low resistance and high ON current, thereby increasing memory capacity without sacrificing electrical performance.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes a first stacked body, a second stacked body, an intermediate conductive layer, an intermediate insulating layer, a semiconductor pillar, a charge storage film, and an insulating film. The semiconductor pillar includes a first part, a second part, and a third part. The charge storage film includes a first charge storage portion and a second charge storage portion. The charge storage film includes at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum. The insulating film provides in at least a portion between the intermediate conductive layer and the first part. The insulating film not includes the first element, or the insulating film has a concentration of the first element lower than a concentration of the first element of the charge storage film.