3D Memory Stack Hydrogen Supply Layer for Transistor Reliability
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Solution Overview
Problem
As semiconductor devices integrate to achieve high performance and multifunctionality, the electrical properties of transistors, particularly in DRAM cells, are compromised due to issues in metal line connections and semiconductor substrate interactions, necessitating improved hydrogen treatments.
Innovation Solution
A semiconductor device design incorporating a first semiconductor structure with a memory region and a second semiconductor structure vertically overlapping the first, featuring a cell hydrogen supply layer and insulating layers to enhance electrical connections and minimize hydrogen diffusion impacts on memory structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hydrogen treatment is performed to improve electrical connection properties, then electrical properties of transistors are improved, but hydrogen diffusion may adversely affect memory structures
Solution Approach 1:
The device is divided into two separate semiconductor structures: a first structure containing the memory structure and a second structure containing the peripheral circuit. This segmentation allows hydrogen treatment to be applied to the peripheral circuit region without directly exposing the memory structure to high hydrogen concentrations, thus improving electrical properties while minimizing harmful hydrogen diffusion effects on memory cells.
Solution Approach 2:
A hydrogen supply layer is introduced as an intermediary component between the memory structure and the peripheral circuit. This layer selectively supplies hydrogen to the peripheral circuit region while acting as a barrier or controlled release mechanism that prevents excessive hydrogen diffusion into the memory structure, thereby mediating between the need for hydrogen treatment and the need to protect memory cells.
2Productivity
If device integration is increased to achieve high performance and multifunctionality, then device performance and functionality are improved, but electrical properties of transistors deteriorate due to metal line connection issues
Solution Approach 1:
The integrated device is segmented into two functional structures: a first semiconductor structure for memory functions and a second semiconductor structure for peripheral circuit functions. This segmentation allows each structure to be optimized independently while maintaining their integrated benefits, resolving the contradiction between high integration and electrical property degradation.
Solution Approach 2:
Different regions of the device are treated with different hydrogen supply characteristics. The peripheral circuit region receives sufficient hydrogen treatment to improve metal line connections and electrical properties, while the memory structure region is protected from excessive hydrogen exposure. This local differentiation of hydrogen supply quality allows high integration performance while maintaining reliable electrical properties in critical regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the electrical properties and reliability of transistors by optimizing hydrogen distribution, reducing interfacial trap densities, and enhancing leakage current properties, thereby stabilizing transistor performance.
Implementation Method 1
a cell hydrogen supply layer, surrounding a portion of the cell routing line structure, between the cell bonding structure and the vertical channel transistor
Data Source
AI summary
A semiconductor device includes a first semiconductor structure having a memory region, and a second semiconductor structure vertically overlapping the first semiconductor structure, the second semiconductor structure having a peripheral circuit region vertically overlapping the memory region. The first semiconductor structure includes a memory structure including a vertical channel transistor disposed in the memory region and an information storage structure disposed on the vertical channel transistor, and a cell routing line structure electrically connected to the memory structure. The second semiconductor structure includes a peripheral circuit disposed in the peripheral circuit region, and a peripheral routing line structure electrically connecting the peripheral circuit and the cell routing line structure to each other. The first semiconductor structure further includes a cell hydrogen supply layer disposed between the memory structure and the second semiconductor structure.