3D Memory Stack I/O Failover for Defective Die Bypass
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Solution Overview
Problem
The likelihood of a defective die adversely affecting a memory device increases with the number of devices in a three-dimensional stack DRAM (3DS DRAM) architecture, leading to potential failures and reduced reliability.
Innovation Solution
The implementation of switched connections and through-silicon vias (TSVs) in a 3DS DRAM device allows for the management of primary data communication, enabling the bypass of defective drive or receive circuitry and the substitution of alternative die I/O circuitry to maintain device functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of devices in the 3DS DRAM stack is increased to improve storage capacity, then storage capacity is improved, but the likelihood of defective dies increases
Solution Approach 1:
The patent segments the I/O circuit functionality across multiple dies in the stack. Each die has its own I/O circuit, and the system can selectively activate I/O circuits from different dies. This segmentation allows the system to bypass defective I/O circuits by activating circuits from other dies, thereby maintaining reliability while increasing storage capacity through additional stacked dies.
2Quantity of substance
If more dies are stacked to increase storage capacity, then storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent implements universal I/O circuitry across all dies in the stack, where each die possesses complete I/O functionality. This multi-functionality allows any die to serve as the active I/O interface, simplifying the overall system architecture by eliminating the need for complex selective activation logic and reducing device complexity despite increased stacking.
3Reliability
If switched connections and TSVs are implemented to enable bypass of defective circuitry, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent introduces TSVs as intermediary vertical interconnect structures that enable communication between dies and facilitate the bypassing of defective I/O circuits. These TSVs act as mediators that allow signal routing around defective components, improving reliability while maintaining relatively simple switch control logic that manages the switched connections.
Solution Approach 2:
The patent implements dynamic switching capability where the system can selectively activate or deactivate specific I/O circuits based on die functionality. This dynamic reconfiguration allows the system to adapt to defects by activating alternative I/O paths, improving reliability while using simple switch control logic to manage the dynamic switching between different die configurations.
Data Source
AI summary
Described are memory systems and devices in which each memory die in a three-dimensional stack of memory dies includes drive and receive circuitry that can communicate data signals from the stack on behalf of all the memory dies in the stack. The drive and receive circuitry, if defective on one device in the stack, can be disabled and substituted with the drive and receive circuitry from another. The stack of memory dies can thus function despite a failure of drive or receive circuitry in one or more of the memory dies. Each memory die includes test circuitry to detect defective drive and receive circuitry.