3D Memory Cell Stack Isolation for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing semiconductor technologies face challenges in achieving high memory cell integration and reducing parasitic capacitance in three-dimensional memory devices.
Innovation Solution
A method for fabricating semiconductor devices involves forming vertical stacks with dielectric and horizontal layer patterns, using cell isolation layers and sacrificial structures to create storage openings, and integrating data storage elements, along with conductive lines and isolation layers to enhance memory cell density and reduce capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically to increase integration density, then memory cell density is improved, but parasitic capacitance increases
Solution Approach 1:
The vertical stack is segmented into multiple memory cells separated by cell isolation layers. Each memory cell is electrically isolated from adjacent cells by these isolation layers, which break up the continuous conductive paths that would otherwise create parasitic capacitance between stacked cells. This allows high density vertical stacking while maintaining low parasitic capacitance through proper segmentation.
Solution Approach 2:
Cell isolation layers act as intermediary structures between adjacent memory cells in the vertical stack. These isolation layers, positioned between the horizontal layer patterns of different memory cells, provide electrical isolation and prevent direct capacitive coupling. The isolation layers mediate the interaction between stacked cells, enabling high density integration while controlling parasitic effects.
2Object-generated harmful factors
If cell isolation layers are formed to reduce parasitic capacitance, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
Cell isolation layers are formed preliminarily during the stack formation process, before final memory cell fabrication. The isolation layers are deposited and patterned early in the manufacturing sequence, establishing the electrical isolation framework that guides subsequent processing steps. This preliminary action simplifies later manufacturing by pre-defining cell boundaries and isolation regions.
Solution Approach 2:
The formation of cell isolation layers is merged with the vertical stack formation process. The isolation layers are integrated into the same manufacturing sequence that creates the alternating dielectric and horizontal layer pattern structure. By combining these operations, the patent reduces the total number of separate fabrication steps while achieving both stack formation and electrical isolation.
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a vertical stack in which dielectric layers are alternately stacked with horizontal layer patterns, over a lower structure; forming cell isolation layers that contact side surfaces of the horizontal layer patterns and vertically extend in the vertical stack; forming a sacrificial structure that covers upper surfaces and lower surfaces of the horizontal layer patterns in the vertical stack; forming a hole-shape opening that vertically extends, by etching the sacrificial structure and the cell isolation layers; forming a double pocket layer on a sidewall of the hole-shape opening; forming storage openings, by recessing the horizontal layer patterns and the cell isolation layers using the double pocket layer as a barrier; and forming a data storage element in each of the storage openings.