Semiconductor Memory Stack Liner for Etch Damage Control
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Solution Overview
Problem
Existing etching processes in semiconductor manufacturing often damage or etch non-volatile memory (NVM) components like the charge-trapping layer and channel layer, leading to defects and reduced production yield.
Innovation Solution
Incorporation of an additional etching stop layer, such as a liner, to protect the charge-trapping and channel layers during etching operations, ensuring minimal damage and improved process control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional etching processes are used to remove sacrificial layers, then the etching process can proceed, but the charge-trapping layer and channel layer are damaged or excessively consumed
Solution Approach 1:
A liner layer is introduced as an intermediary between the sacrificial layer and the charge-trapping/channel layers. This liner acts as a protective mediator that allows the etching process to remove the sacrificial layer while preventing direct contact and damage to the underlying NVM components. The liner is selectively removed after serving its protective function.
Solution Approach 2:
The liner layer is deposited in advance before the etching process begins. This preliminary protective action ensures that the charge-trapping and channel layers are already protected before the harmful etching process starts, preventing damage from occurring in the first place rather than attempting to fix it afterward.
2Device complexity
If etching process is performed without additional protection, then the process is simpler, but defects increase and production yield decreases
Solution Approach 1:
The liner layer is designed as a temporary, disposable protective element that is discarded after serving its purpose. It is deposited to protect during etching, then selectively removed in a subsequent process step. This approach accepts the added complexity of the liner deposition and removal steps as a necessary investment to achieve significantly improved production yield and reduced defects.
3Speed
If the etching process is performed aggressively to remove sacrificial layers quickly, then the etching speed increases, but the charge-trapping layer and channel layer are excessively consumed
Solution Approach 1:
The liner layer serves as a sacrificial intermediary that absorbs the aggressive etching action. The etch process is directed at removing the liner and the sacrificial layer it protects, rather than directly attacking the charge-trapping and channel layers. This allows for faster, more aggressive etching speeds without excessive consumption of the critical NVM layers.
Data Source
AI summary
A method includes: depositing charge-trapping layers over a substrate; depositing channel layers over the charge-trapping layers; forming a plurality of first filling regions between the channel layers, the first filling regions including first trenches; depositing a liner over upper surfaces of the charge-trapping layers and the channel layers and sidewalls of the first trenches; forming second filling regions in the first trenches; and removing at least part of the liner and the second filling regions to expose the charge-trapping layers and the channel layers.