Stair Step Memory Stack With Liner Trimming for Contact Accuracy
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Solution Overview
Problem
Conventional vertical memory arrays face challenges in increasing memory density without increasing the overall width of the stack structure, leading to complex and congested routing paths, and improper formation of conductive contacts due to the staircase structure's height, resulting in potential array failures.
Innovation Solution
A method of forming microelectronic devices with stair step regions comprising vertically alternating conductive and insulative structures, where a liner material is formed over the steps, and laterally extending portions of the liner material are removed to improve the accuracy of electrically conductive contact placement, facilitating proper contact formation with the conductive structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the quantity of tiers of conductive structures is increased to provide additional memory density, then memory density is improved, but the routing paths become complex and congested
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by forming stair step structures that extend vertically. Conductive contact structures are positioned on different vertical levels (steps) to access different tiers of conductive structures, enabling routing in the vertical dimension rather than only in the horizontal plane. This reduces horizontal congestion while accommodating increased memory density.
2Quantity of substance
If the height of the staircase structure is increased to access additional tiers, then memory density is improved, but the conductive contacts may not be properly formed
Solution Approach 1:
The stair step structure is segmented into discrete steps, each providing a distinct contact region for accessing a specific tier of conductive structures. This segmentation breaks down the complex task of forming contacts to multiple tiers into manageable individual steps, where each step can be independently formed and controlled, thereby maintaining manufacturing precision even as the overall structure height increases.
3Quantity of substance
If the quantity of steps in individual staircase structures is increased, then memory density is improved, but the overall width of the stack structure increases
Solution Approach 1:
Instead of expanding the stack structure width horizontally to accommodate additional steps, the patent utilizes the vertical dimension by forming multiple tiers of conductive structures at different heights. The stair step structures extend vertically with steps at different elevation levels, allowing access to multiple tiers without increasing the lateral footprint of the device.
4Quantity of substance
If conventional vertical memory arrays are used, then memory density is improved, but the routing paths become congested and reliability decreases
Solution Approach 1:
The patent employs three-dimensional stair step structures that route connections vertically through multiple levels, distributing the routing load across the vertical dimension. This prevents horizontal congestion and reduces the risk of routing failures, thereby improving overall array reliability while maintaining high memory density.
Data Source
AI summary
A microelectronic device comprises a first deck structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, a second deck structure vertically overlying the first deck structure and comprising additional tiers of the conductive structures and insulative structures, a staircase structure within the first deck structure and having steps comprising edges of the tiers, a dielectric material covering the steps of the staircase structure and extending through the first deck structure, and a liner material interposed between the steps of the staircase structure and terminating at an interdeck region between the first deck structure and the second deck structure. Related microelectronic devices, electronic systems, and methods are also described.