3D Memory Stack Pad Layout for Compact Multi-Layer Connections
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Solution Overview
Problem
The complexity of manufacturing processes and internal connections in three-dimensional flash memory devices makes it challenging to achieve a compact and efficient design, particularly in connecting multi-stack memory structures with peripheral circuits.
Innovation Solution
A memory device design that includes a substrate with stacked first and second memory structures, connected through an inter-metal layer and an upper metal layer, allowing for electrical coupling of word lines to a peripheral circuit, thereby reducing the complexity of layer connections and device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional stacked memory structures are used to increase storage capacity, then memory density is improved, but manufacturing process complexity and internal connection complexity increase
Solution Approach 1:
The memory device is divided into multiple independent memory stacks (first memory structure and second memory structure) that can be manufactured and connected separately. Each stack has its own word lines and connection pads, allowing modular manufacturing and reducing overall process complexity while maintaining high storage capacity.
Solution Approach 2:
The patent transitions from planar two-dimensional memory layout to three-dimensional stacked architecture with multiple layers (substrate, inter-metal layer, upper metal layer). Word lines are stacked vertically across different layers, enabling increased storage density by utilizing the vertical dimension rather than only horizontal expansion.
2Adaptability or versatility
If multiple memory stacks are connected through the same metal layer, then connectivity is achieved, but the layout becomes complex and device size increases
Solution Approach 1:
Connection pads are segmented into different metal layers: intermediate pads in the inter-metal layer connect to first word lines, while upper pads in the upper metal layer connect to second word lines. This layer-specific segmentation allows multiple memory stacks to be connected through different layers, reducing layout complexity and device size.
Solution Approach 2:
The inter-metal layer acts as an intermediary between the substrate and the upper metal layer, providing intermediate connection pads that facilitate connections from first word lines. This intermediary layer enables complex three-dimensional routing while maintaining a compact layout by distributing connections across multiple layers rather than requiring all connections in a single plane.
Data Source
AI summary
A memory device includes a peripheral circuit layer, a first memory layer provided on the peripheral circuit layer, an inter-metal layer provided on the first memory layer, and a second memory layer provided on the inter-metal layer. The peripheral circuit layer includes a first substrate and a peripheral circuit provided on the first substrate. The first memory layer includes a first memory structure electrically connected to the peripheral circuit through metal bonding pads. The inter-metal layer includes intermediate pads electrically connected to the peripheral circuit through metal bonding pads. The second memory layer includes a second memory structure electrically connected with the intermediate pads and a second substrate provided on the second memory structure. The peripheral circuit, the first memory structure, and the second structure are provided between the first substrate and the second substrate.