3D Semiconductor Memory Stack With Passthrough Columns for Heat Control
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Solution Overview
Problem
Manufacturers face challenges in reducing the space occupied by semiconductor devices while increasing capacity and speed of operation, particularly in processing applications where interconnections with multiple devices and significant power supplies generate excessive heat.
Innovation Solution
The semiconductor device assemblies stack intermediary devices vertically between a processing device and an assembly substrate, utilizing passthrough conductive columns for direct electric communication, reducing the need for lateral spacing and interconnections, and minimizing heat exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If semiconductor devices are arranged laterally adjacent to one another, then interconnections between devices can be established, but the assembly footprint increases and heat management becomes more difficult
Solution Approach 1:
The patent transitions from a two-dimensional lateral arrangement of semiconductor devices to a three-dimensional vertical stacking configuration. Multiple semiconductor devices are stacked vertically with interconnections formed through the stack using conductive vias and traces on intermediate substrates, thereby reducing the assembly footprint while maintaining necessary interconnections through vertical routing paths.
Solution Approach 2:
The patent introduces intermediate substrates (carrier substrates or support structures) that serve as mediators between stacked semiconductor devices. These intermediaries provide routing layers with conductive traces and vias that establish electrical connections between devices in different vertical layers, simplifying the interconnection architecture compared to direct device-to-device bonding.
2Area of stationary object
If processing devices are combined with multiple support devices in a compact assembly, then space is reduced, but heat generation from power supplies exposes elements to excessive heat
Solution Approach 1:
The patent arranges semiconductor devices in vertical stacks separated by intermediate substrates, creating vertical spacing that facilitates heat dissipation pathways. High-power processing devices can be positioned at different vertical levels with thermal management structures (heat sinks, thermal vias, or cooling channels) integrated into the intermediate substrates, allowing heat to conduct vertically rather than concentrating in a compact lateral arrangement.
Solution Approach 2:
The intermediate substrates serve as thermal mediators between stacked devices, providing thermal management functions such as heat spreading layers, thermal vias, or integrated heat sinks. These intermediaries conduct heat away from high-power devices and distribute it to cooling structures, reducing heat exposure to sensitive elements while maintaining the compact vertical assembly.
3Area of stationary object
If lateral spacing is reduced to minimize assembly size, then footprint is reduced, but signal transmission quality deteriorates
Solution Approach 1:
The patent routes signals vertically through intermediate substrates using conductive traces and vias, separating signal paths from lateral spacing constraints. This vertical routing through controlled-impedance transmission lines on intermediate substrates maintains signal integrity even when lateral device spacing is minimized, as the signal path length and coupling are controlled by the substrate design rather than lateral proximity.
Data Source
AI summary
A semiconductor device assembly can include an assembly substrate having a top surface, a top semiconductor device having a bottom surface, and a plurality of intermediary semiconductor devices. Each of intermediary semiconductor device can be bonded to both the assembly substrate top surface and the top device bottom surface. Each intermediary semiconductor device can also include a semiconductor substrate, a memory array, a first bond pad, a second bond pad, and a conductive column. The first bond pad can electrically couple the assembly substrate to the intermediary semiconductor device; the second bond pad can electrically couple the top semiconductor device to the intermediary semiconductor device; and the conductive column can electrically couple the first bond pad to the second bond pad, and can be exclusive of any electrical connection to the memory array.