3D Memory Stack Contact Plug Isolation With Sealing Layers

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Solution Overview

Problem

The integration of memory cells in two-dimensional semiconductor devices has reached its limit, necessitating the development of three-dimensional memory devices with stacked memory cells, where the formation of contact plugs faces challenges such as punching failure due to the stepped shape of the stack structure, which complicates the etching process and increases the risk of contact plugs connecting undesirably with underlying gate electrode layers.

Innovation Solution

A semiconductor device and fabrication method involving a stack structure with alternately stacked sacrificial layers and dielectric layers, where sacrificial pads and sealing layers are used to prevent physical and electrical connections between gate electrode layers and contact plugs, allowing for precise control of etching and reducing the risk of punching failure by separating the contact plugs from the underlying layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If contact plugs are formed to pass through the stack structure in a three-dimensional memory device, then electrical connection to gate electrode layers is achieved, but punching failure occurs due to the stepped shape complicating the etching process

Engineering Contradiction:
Improvecontact plug formation reliabilityVSAvoidetching process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A sealing layer pattern is introduced as an intermediary element between the contact plugs and the gate electrode layers. This sealing layer pattern prevents direct contact between the contact plugs and undesired gate electrode layers, thereby eliminating punching failure without requiring complex etching process control. The sealing layer acts as a mediator that simplifies the etching process while ensuring reliable electrical connections.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sealing layer pattern is formed in advance before the contact plugs are created. This preliminary action prepares the structure by establishing protective barriers at critical interfaces, allowing subsequent etching and contact plug formation to proceed with simpler processes and higher reliability, as the sealing layer already prevents potential punching failures.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the stack structure is formed with alternately stacked conductive layers and dielectric layers, then three-dimensional memory cells are achieved, but the stepped shape increases the risk of contact plugs connecting undesirably with underlying gate electrode layers

Engineering Contradiction:
Improvememory cell integration densityVSAvoidcontact plug connection control
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The sealing layer pattern serves as an intermediary barrier that prevents undesired direct connections between contact plugs and gate electrode layers. This allows the stack structure to maintain its high integration density three-dimensional configuration while the sealing layer ensures reliable control over contact plug connections by blocking unintended electrical paths.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sealing layer pattern is selectively applied at specific locations where contact plugs are formed, providing localized protection against undesired connections. This local quality approach maintains the overall three-dimensional stacked structure for high density while adding targeted control elements only where needed to prevent punching failures.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240030141A1Semiconductor device, method for fabricating the semiconductor device, and memory device and system including the semiconductor device
Publication Date: 2024.01.25 SK HYNIX INC
  • US20240030141A1 patent drawing
  • US20240030141A1 patent drawing
  • US20240030141A1 patent drawing

AI summary

A semiconductor device according to an embodiment of the present disclosure may include: a stack structure including a plurality of first conductive patterns and a plurality of dielectric layers, which are alternately stacked, the stack structure having a stepped structure such that any one of the first conductive patterns further protrudes than the first conductive pattern positioned immediately above it; a plurality of second conductive patterns which are respectively formed over protrusions of the first conductive patterns; a plurality of contact plugs which overlap the plurality of second conductive patterns, respectively, and pass through the overlapping second conductive patterns and the stack structure; and a sealing layer pattern which is interposed between the first conductive patterns and the contact plugs and separates the first conductive patterns from the contact plugs.