3D Memory Stack Layout With Drain Select Plug Separation
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Solution Overview
Problem
Existing semiconductor memory devices with nonvolatile memory technology face challenges in achieving high write and read speeds while maintaining data integrity even when power is cut off.
Innovation Solution
A semiconductor memory device with a vertical channel structure is designed, featuring a lower stack with alternating interlayer insulating and conductive layers, cell plugs, an upper stack with additional interlayer insulating and conductive layers, drain select plugs, and a separation pattern that separates adjacent drain select plugs, enabling efficient separation of select lines in the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a vertical channel structure is used to improve write and read speeds, then access speed is improved, but device complexity increases due to the need for separation patterns and multiple stacked layers
Solution Approach 1:
The memory device is divided into distinct stacked segments (lower stack, upper stack) with separate select line regions. The separation pattern divides the select line into first and second select lines, allowing independent control of different memory regions. This segmentation enables faster access by parallelizing operations across segments while managing complexity through modular design.
Solution Approach 2:
The patent transitions from a planar memory structure to a three-dimensional vertical stack architecture. Multiple conductive layers and interlayer insulating layers are stacked vertically to create word lines, bit lines, and select lines in the vertical dimension. This dimensional change increases storage capacity and access speed without proportionally increasing planar footprint, though it does increase vertical structural complexity.
2Quantity of substance
If multiple conductive layers and interlayer insulating layers are stacked to increase storage capacity, then quantity of substance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The stacked structure is divided into lower and upper stacks, each with their own conductive layers and interlayer insulating layers. This segmentation allows for controlled formation of multiple layers through sequential processing steps, making the manufacturing of high-capacity 3D structures more manageable and precise.
Solution Approach 2:
The separation pattern is formed before final plug formation to pre-establish the division between first and second select lines. This preliminary action ensures proper alignment and spacing of subsequent layers, reducing the precision requirements for later manufacturing steps and enabling accurate formation of multiple stacked conductive layers.
3Reliability
If select lines are separated into first and second select lines using a separation pattern, then reliability is improved through better control, but device complexity increases
Solution Approach 1:
The select line is divided into first and second select lines by the separation pattern, enabling independent control of different memory cell arrays or regions. This segmentation improves reliability by allowing selective access and independent operation of memory blocks, reducing interference and enabling better error management, while the added structural element is managed through systematic design.
Solution Approach 2:
The separation pattern acts as an intermediary structure that physically and electrically divides the select line into separate segments. This intermediary element provides controlled isolation between first and second select lines, ensuring signal integrity and preventing cross-talk, thereby improving data reliability while adding a manageable structural component.
Data Source
AI summary
A semiconductor memory device, and a method of manufacturing the same, includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs passing through the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs passing through the upper stack and being in contact with an upper portion of the plurality of cell plugs, and a separation pattern separating adjacent drain select plugs among the plurality of drain select plugs, wherein the separation pattern is in contact with a sidewall of each of the adjacent drain select plugs.