3D Non-Volatile Memory Stack With Shared Inter-Die Power Routing
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Solution Overview
Problem
Current memory designs lack sufficient space and flexibility to accommodate all power demands, leading to design compromises, as power lines are typically designed for each die separately rather than considering the entire stack of memory systems.
Innovation Solution
The proposed solution involves designing power lines for the entire stack of memory systems to share power among different dies, utilizing a stack of integrated memory assemblies where each assembly includes a memory die bonded to a control die, with conductive vias extending through the substrate to route power signals between dies, allowing for improved powerline efficiency and strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more capacity and functionality are added to memory, then memory capacity increases, but power consumption increases and die space is reduced
Solution Approach 1:
The memory system is divided into multiple separate dies, each containing a portion of the total memory capacity. This segmentation allows the power delivery network to be distributed across multiple smaller units rather than requiring a single large power network, thereby managing power consumption more effectively while achieving high total capacity.
Solution Approach 2:
The patent transitions from a two-dimensional layout to a three-dimensional stacked architecture where multiple dies are vertically arranged. This dimensional change enables increased memory capacity without proportionally increasing the footprint area, and allows shared power networks to serve multiple dies efficiently through vertical interconnections.
2Quantity of substance
If more capacity and functionality are added to memory, then memory capacity increases, but die space available for other functions is reduced
Solution Approach 1:
The total memory capacity is distributed across multiple separate dies rather than concentrated on a single large die. This segmentation frees up die space on each individual die for other functions while achieving high total capacity through the combination of multiple dies in a stack.
Solution Approach 2:
By stacking multiple dies vertically, the patent increases memory capacity in the vertical dimension rather than expanding horizontally. This allows each die to maintain a compact footprint with space for additional functions, while the overall system achieves high capacity through the stacked configuration.
3Ease of manufacture
If power lines are designed for each die separately, then design simplicity is maintained, but powerline efficiency and flexibility are reduced
Solution Approach 1:
The power network is designed as a shared universal infrastructure that serves multiple dies simultaneously. Power lines and distribution networks are configured to provide power to several dies through the stacked interconnections, increasing flexibility and adaptability while maintaining manageable design complexity through standardized power delivery architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances system powerline efficiency and strength by allowing power signals to be shared between dies, reducing the need for additional power lines and improving overall memory system performance.
Implementation Method 1
The substrate comprises a set of conductive vias that extend completely through the substrate. These vias connect at one end to the top metal layer of the memory die of an adjacent integrated memory assembly and connect at a second end to the set of metals layers above the control circuit
Data Source
AI summary
A non-volatile memory apparatus comprises a stack of integrated memory assemblies. Each integrated memory assembly includes a memory die bonded to a control die and a set of power pads connected to metal lines in the respective memory die and control die. The memory dies comprise a non-volatile memory structure and a top metal layer for transmitting power signals above the memory structure. The control dies comprise a substrate, a control circuit positioned on the substrate for performing memory operations on a corresponding memory structure and a set of metals layers above the control circuit. The substrate comprises a set of conductive vias through the substrate that connect at one end to the top metal layer of the memory die of an adjacent integrated memory assembly and connect at a second end to the set of metals layers above the control circuit for routing signals between integrated memory assemblies.