3D Memory Stack Sacrificial Sidewalls for Stable Support Structures
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Solution Overview
Problem
The integration degree of two-dimensional nonvolatile memory elements has reached its limit, necessitating the development of three-dimensional structures with improved reliability, which poses challenges in maintaining data stability and manufacturing efficiency.
Innovation Solution
A semiconductor device with alternately stacked interlayer insulating and gate conductive layers, channel plugs, support structures, and a sacrificial layer is designed, featuring a method of manufacturing that includes forming trenches and stacks on a substrate to create stable contact and cell regions, enhancing the structural integrity and manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional nonvolatile memory elements are used to improve manufacturing simplicity, then manufacturing ease is improved, but integration degree reaches its limit and cannot be further improved
Solution Approach 1:
The patent transitions from two-dimensional memory element layout to three-dimensional stacked structures by introducing vertical channel plugs that pass through multiple interlayer insulating layers and gate electrodes. This dimensional change enables stacking multiple memory cells vertically, thereby increasing integration degree while maintaining manufacturing feasibility through sequential layer formation processes
2Quantity of substance
If three-dimensional nonvolatile memory elements with stacked structures are used to improve integration degree, then integration degree is improved, but structural complexity increases
Solution Approach 1:
The three-dimensional memory structure is segmented into repeating units consisting of interlayer insulating layers and gate electrodes stacked alternately, with channel plugs passing through these segments. This segmentation creates modular memory cells that can be stacked vertically, increasing integration while maintaining manageable structural complexity through repetitive patterns
Solution Approach 2:
The patent implements nested structures where channel plugs are surrounded by memory cell structures, which are in turn surrounded by stacked interlayer insulating layers and gate electrodes. This nesting arrangement maximizes space utilization and increases integration degree while organizing complexity in a hierarchical manner
3Quantity of substance
If three-dimensional stacked structures are used to improve integration degree, then integration degree is improved, but reliability of data storage may be compromised
Solution Approach 1:
Interlayer insulating layers are inserted between stacked gate electrodes and channel plugs to provide electrical isolation and mechanical cushioning. These insulating layers prevent unwanted electrical interactions between adjacent memory cells and protect against defects propagating vertically through the stack, thereby maintaining reliability in three-dimensional structures
Data Source
AI summary
The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a stack including a plurality of interlayer insulating layers and a plurality of gate conductive layers alternately stacked, a channel plug formed on a cell region by vertically passing through the stack, a plurality of support structures formed on a contact region by vertically passing through the stack, and a sacrificial layer surrounding a lower end portion sidewall of each of the plurality of support structures.