Memory Stack Segmentation for Vertical Integration Stability
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Solution Overview
Problem
The challenge in semiconductor devices is to prevent the leaning or falling of memory stack structures as the number of word line stacks increases, which can lead to process defects and reduced reliability during manufacturing, especially when enhancing the degree of integration and increasing the height of the word line stack.
Innovation Solution
The implementation of a semiconductor device design that includes a peripheral circuit structure with a memory stack structure featuring gate lines overlapping in a vertical direction, an interlayer insulation layer, a dam structure, an intersection direction cut structure, and dummy channel structures to stabilize the memory stack and reduce stress caused by the interlayer insulation layer, thereby preventing deformation and process defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word line stacks increases to enhance the degree of integration, then the data storage capacity is improved, but the height of the word line stack increases causing leaning or falling of the memory stack structure
Solution Approach 1:
The memory stack structure is divided into multiple memory cell blocks, each independently supported by dummy channel structures. This segmentation prevents the entire stack from leaning or falling by distributing structural support across multiple sections, allowing increased integration while maintaining stability.
Solution Approach 2:
Dummy channel structures are introduced as intermediary elements between the gate lines and the substrate. These dummy channels act as support pillars that prevent the memory stack structure from leaning or falling, enabling higher integration without compromising structural integrity.
2Quantity of substance
If the height of the word line stack increases for enhanced integration, then the data storage capacity is improved, but process defects increase due to leaning or falling of the memory stack structure
Solution Approach 1:
Dummy channel structures are formed before the memory stack structure is fully assembled. This preliminary action provides structural support in advance, preventing leaning or falling during subsequent manufacturing processes and reducing process defects even as stack height increases.
Solution Approach 2:
The dummy channel structures serve as intermediary support elements that stabilize the memory stack during manufacturing. By introducing these intermediate support structures, the patent prevents process defects caused by stack deformation while maintaining the ability to increase integration density.
3Quantity of substance
If the number of word line stacks increases to enhance integration, then the data storage capacity is improved, but reliability decreases due to leaning or falling of the memory stack structure
Solution Approach 1:
The memory stack is segmented into multiple memory cell blocks with independent support structures. This segmentation ensures that if one section experiences stress, other sections remain stable, thereby maintaining overall device reliability even as the total number of stacks increases for higher capacity.
Solution Approach 2:
Dummy channel structures act as intermediary support elements that enhance the reliability of the memory stack structure. By providing additional support points, these dummy channels prevent leaning or falling that would otherwise compromise device reliability, enabling safe increases in integration density.
Data Source
AI summary
Semiconductor devices may include a peripheral circuit structure including circuits, a substrate on the peripheral circuit structure, a pair of word line cut structures extending in a first direction on the substrate, and a memory cell block between the pair of word line cut structures and on the substrate. The memory cell block may include a memory stack structure including gate lines overlapping each other in a vertical direction, an interlayer insulation layer on an edge portion of each of the gate lines, a dam structure extending through the gate lines and the interlayer insulation layer, an intersection direction cut structure extending through the memory stack structure and the interlayer insulation layer in the vertical direction and being spaced apart from the dam structure, and a dummy channel structures between the intersection direction cut structure and the dam structure.