3D Memory Stack Structure with Shared Control Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor device designers face challenges in increasing integration density and reducing fabrication costs due to complications in electrically connecting multiple decks of 3D memory arrays to control logic devices, which impede size reduction and storage density improvements.
Innovation Solution
A semiconductor device with a stack structure comprising decks where each deck includes a memory level between a control logic level and an additional control logic level, allowing for shared control operations and differentiated control logic devices, facilitating efficient electrical communication through a base control logic structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of decks in a 3D memory array is increased to improve storage density, then storage capacity increases, but the complexity of routing and interconnect structures increases, creating sizing and spacing complications
Solution Approach 1:
The patent transitions from a conventional 2D memory array to a 3D stack structure with multiple decks vertically stacked. Memory cells are arranged in three dimensions with word lines extending vertically through multiple decks, enabling increased storage density without proportionally increasing lateral routing complexity. The vertical stacking allows memory capacity to scale by adding decks rather than expanding lateral footprint.
Solution Approach 2:
The memory array is segmented into multiple decks, each containing a subset of memory cells. Control logic is divided into base control logic and deck-specific control logic, with each deck independently controllable. This segmentation allows modular scaling where additional decks can be added without redesigning the entire control structure, managing complexity through hierarchical organization.
2Adaptability or versatility
If more control logic devices are added to control operations on multiple decks, then control capability improves, but the size of the memory device increases and fabrication costs increase
Solution Approach 1:
The base control logic structure is designed to be universal and shared across all decks. Word line control signals and basic control logic functions are common to multiple decks, allowing the same control circuitry to manage operations on different decks without requiring duplicate control logic for each deck. This multi-functionality reduces the total number of control devices needed.
Solution Approach 2:
Control logic functions are merged between base control logic and deck control logic. The base control logic handles common operations for all decks, while deck control logic handles deck-specific operations. This merging eliminates redundancy and allows compact integration where control logic serves multiple purposes across different memory decks.
Data Source
AI summary
A semiconductor device comprises a stack structure comprising decks each comprising a memory level comprising memory elements, a control logic level vertically adjacent and in electrical communication with the memory level and comprising control logic devices configured to effectuate a portion of control operations for the memory level, and an additional control logic level vertically adjacent and in electrical communication with the memory level and comprising additional control logic devices configured to effectuate an additional portion of the control operations for the memory level. A memory device, a method of operating a semiconductor device, and an electronic system are also described.