3D Memory Stack Grooves With Sidewall Steps for Contact Formation
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Solution Overview
Problem
The existing manufacturing processes for three-dimensional semiconductor memory devices are complex and inefficient, particularly in forming connection regions, which hinders the integration and performance of these devices.
Innovation Solution
A semiconductor memory device and manufacturing method involving a substrate with stacked structures, including lower, intermediate, and upper layers, where grooves are etched to expose different depths of lower layers, and steps are formed along the groove sidewalls to simplify the connection region formation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing manufacturing processes are used for three-dimensional semiconductor memory devices, then connection regions can be formed, but the manufacturing process becomes complex and inefficient
Solution Approach 1:
The connection region formation process is segmented into multiple etching stages, where different etching depths are performed sequentially to expose different lower layers at different depths. This segmentation allows complex three-dimensional connection regions to be formed through simplified, repeated basic operations rather than a single complex process step.
Solution Approach 2:
The method performs preliminary etching actions to expose lower layers before final contact plug formation. By pre-exposing the lower layers at appropriate depths and forming steps along sidewalls in advance, the subsequent connection region formation becomes simpler and more efficient.
2Productivity
If grooves are etched to expose lower layers at different depths, then connection regions are simultaneously exposed, but the etching process becomes more complex
Solution Approach 1:
Multiple etching operations are merged into a unified process flow where the same etching apparatus and methodology are used repeatedly for different etching depths. This merging of process steps into a standardized, repeatable sequence improves productivity while managing complexity through process integration rather than diversification.
Solution Approach 2:
The etching process employs periodic action by repeating the cycle of etching to a specific depth, forming steps along sidewalls, and then continuing to etch deeper. This periodic repetition of standardized operations enables simultaneous exposure of multiple lower layers at different depths while maintaining process simplicity through rhythm and pattern.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process by allowing simultaneous exposure of connection regions at different depths, reducing the complexity and enhancing the integration and performance of three-dimensional semiconductor memory devices.
Implementation Method 1
etching the third stack structure such that reference regions respectively exposing upper surfaces of the upper layers are defined; forming a plurality of grooves respectively opening upper surfaces of the lower layers
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. A semiconductor memory device includes a lower stack structure on the substrate and including a plurality of lower layers stacked in a vertical direction, an intermediate stack structure on the lower stack structure and including a plurality of intermediate layers stacked in the vertical direction, a plurality of grooves in the contact region and penetrating the intermediate stack structure, the plurality of grooves exposing the lower stack structure at different depths, and a plurality of steps formed along sidewalls of the grooves.