3D Memory Stack Slit Structure for Stable Region Separation
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Solution Overview
Problem
The integration density of two-dimensional non-volatile memory devices is limited, leading to the development of three-dimensional non-volatile memory devices with stacked memory cells, which require improved structural stability and manufacturing methods to enhance operational reliability.
Innovation Solution
A semiconductor device with a stacked structure featuring alternating conductive and insulating layers, sacrificial layers, and slit structures with through portions and protrusions to separate regions, along with a manufacturing method that includes forming slits, etching sacrificial layers, and creating conductive layers to support the structure and enhance separation between regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional non-volatile memory devices are used, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional stacked memory cells, where multiple memory cell layers are vertically stacked over the substrate. This dimensional change enables significantly higher integration density by utilizing the vertical space above the substrate rather than only the horizontal plane.
Solution Approach 2:
The memory device is segmented into multiple functional layers including alternating conductive layers and insulating layers, with channel layers passing through vertically. Each layer serves a specific function, and the segmented structure allows for systematic stacking to achieve high integration density while maintaining manufacturability through modular fabrication processes.
2Productivity
If three-dimensional stacked memory cells are implemented, then integration density improves, but structural stability deteriorates
Solution Approach 1:
The patent employs composite material structures with alternating conductive layers and insulating layers, where each material provides specific mechanical and electrical properties. The insulating layers act as spacers and structural support, while the conductive layers provide electrical functionality. This composite approach enhances overall structural stability while maintaining the three-dimensional stacked configuration for high integration density.
Solution Approach 2:
Different regions of the stacked structure have locally optimized properties - the insulating layers provide mechanical support and spacing in regions where structural stability is critical, while the conductive layers are positioned where electrical functionality is required. The channel layers are selectively formed to pass through specific regions, creating local quality variations that simultaneously achieve structural stability and functional performance.
3Productivity
If three-dimensional stacked memory cells are implemented, then integration density improves, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary actions in the manufacturing process by first forming the insulating layers and sacrificial layers in alternating stacks before forming the conductive layers. The sacrificial layers are pre-positioned to define future channel layer locations, and etch holes are formed in advance to guide subsequent material deposition. This preliminary structuring simplifies the overall manufacturing of the complex three-dimensional stacked memory cells.
Solution Approach 2:
The patent uses sacrificial layers as intermediary elements during manufacturing. These sacrificial layers are temporarily formed between the insulating layers to define the positions of future channel layers. During fabrication, etch holes are formed through the sacrificial layers, and conductive materials are deposited. The sacrificial layers are then removed, leaving the desired channel layer structure. This intermediary approach simplifies the manufacturing of complex three-dimensional structures by breaking down the process into manageable sequential steps.
Data Source
AI summary
A semiconductor device includes a stacked structure including a first region in which conductive layers and the insulating layers are stacked alternately with each other, and a second region in which sacrificial layers and the insulating layers are stacked alternately with each other, a first slit structure located at a boundary between the first region and the second region and including a first through portion passing through the stacked structure and first protrusions extending from a sidewall of the first through portion, a second slit structure located at the boundary and including a second through portion passing through the stacked structure and second protrusions extending from a sidewall of the second through portion and coupled to the first protrusions, a circuit located under the stacked structure, and a contact plug passing through the second region of the stacked structure and electrically connected to the circuit.