3D Memory Stack Layout With Split Conductive Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face challenges in shrinking size while maintaining efficiency and reducing manufacturing costs, particularly in the design of conductive layers and contact regions within the memory array and staircase contact regions.
Innovation Solution
A memory device with a stacked structure featuring conductive layers and insulating layers arranged in a longitudinal direction, where the first conductive layers surround a first element structure, and the second conductive layer has conductive portions separated by the first element structure, allowing for a more efficient and cost-effective design by reducing the number of conductive pillars and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the number of conductive pillars is reduced to simplify the manufacturing process, then the ease of manufacture is improved, but the electrical connectivity and device performance may be compromised
Solution Approach 1:
The patent combines multiple conductive layer functions into a unified stacked structure where first conductive layers and a second conductive layer are vertically integrated. This merging reduces the need for separate conductive pillars while maintaining electrical connectivity through the stacked conductive layers that surround the first element structure.
Solution Approach 2:
The patent transitions from a planar arrangement of conductive pillars to a three-dimensional stacked structure with conductive layers arranged in a longitudinal direction. This dimensional change allows electrical connectivity to be achieved through vertical stacking rather than horizontal pillar connections, simplifying the manufacturing process while maintaining reliability.
2Area of stationary object
If the memory device size is shrunk to meet market demand, then the area is reduced, but the manufacturing precision and operational efficiency may deteriorate
Solution Approach 1:
The patent employs a vertical stacked structure with conductive layers and insulating layers arranged in a longitudinal direction, transitioning from two-dimensional planar scaling to three-dimensional vertical integration. This allows area reduction while maintaining manufacturing precision by utilizing the vertical dimension for device functionality.
Solution Approach 2:
The patent implements a nested structure where first conductive layers and a second conductive layer are arranged concentrically around a first element structure. This nesting approach maximizes space utilization and maintains manufacturing precision by organizing multiple functional layers in a compact vertical configuration.
3Volume of moving object
If the conductive layers are arranged in a stacked configuration to improve density, then the volume efficiency is improved, but the device complexity increases
Solution Approach 1:
The patent segments the conductive structure into distinct first conductive layers and a second conductive layer, each performing specific functions. This segmentation allows for modular manufacturing and simplifies the overall device complexity by dividing the stacked structure into manageable functional units that can be fabricated separately and integrated.
Solution Approach 2:
The stacked conductive layers serve multiple functions: the first conductive layers provide lateral connectivity while the second conductive layer provides vertical connectivity, and both layers participate in forming the memory device's electrical pathways. This multi-functionality reduces the need for additional separate structures, thereby reducing overall device complexity despite the stacked configuration.
Data Source
AI summary
A memory device includes a stacked structure and at least one first element structure. The stacked structure is in a memory array region and a staircase contact region. The stacked structure includes first conductive layers and a second conductive layer arranged in a longitudinal direction. The memory array region and the staircase contact region are arranged in a first lateral direction. The at least one first element structure passes through the first conductive layers and the second conductive layer along the longitudinal direction. The first conductive layers surround a sidewall surface of the at least one first element structure. The second conductive layer includes conductive portions arranged in a second lateral direction. The conductive portions are completely separated from each other by the at least one first element structure. The first lateral direction is different from the second lateral direction.