3D Memory Stack Stair Structure for Compact Contact Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently controlling the height of stair portions in contact regions, which affects chip area and manufacturing complexity.
Innovation Solution
The semiconductor device incorporates a design where the height of the stair portion in the contact region is controlled by forming a first and second stacked body with specific stair-like shapes, allowing for reduced chip area and simplified manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the height of stair portions in contact regions is not controlled, then the chip area increases, but the manufacturing complexity remains high
Solution Approach 1:
The patent applies preliminary action by forming the stair portions of the first and second contact regions at different heights during the manufacturing process, rather than attempting to modify them later. This is achieved through selective etching and deposition steps that create the height difference as an inherent feature of the fabrication process, thereby reducing both chip area and manufacturing complexity simultaneously
Solution Approach 2:
The patent utilizes the vertical dimension (Z-axis) by creating stair portions at different heights instead of only varying horizontal positions. This dimensional approach allows for more efficient space utilization in the contact regions, reducing the overall chip area while maintaining manufacturing feasibility through controlled vertical structuring
2Ease of manufacture
If the stair portions are formed at the same height, then the manufacturing process is simpler, but the chip area increases
Solution Approach 1:
The patent performs preliminary actions during fabrication to establish the height difference of stair portions through selective etching and material deposition. This approach integrates the height differentiation into the manufacturing flow itself, making the process manageable while achieving compact chip area utilization
Solution Approach 2:
The patent applies local quality by giving different heights to specific stair portions (first contact region vs. second contact region) based on their local functional requirements. This localized differentiation optimizes space in critical areas without requiring complex global restructuring of the entire chip
Data Source
AI summary
According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.