3D Memory Stack Staircase Structure for Dense, Precise Formation
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Solution Overview
Problem
Conventional methods for forming vertical memory arrays in microelectronic devices, such as 3D NAND Flash memory devices, face challenges with increased feature packing density and reduced margins for fabrication errors, leading to undesirable defects that diminish performance, reliability, and durability.
Innovation Solution
A method involving a preliminary stack structure with alternating sacrificial and insulative materials, forming stadium structures with staircase structures and filled trenches, followed by replacement with conductive materials and dielectric liners, to create a stack structure with conductive and insulative tiers separated by dielectric slot structures, enhancing electrical access and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication methods are used to form staircase structures for electrical connections, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to increased feature packing density and reduced margins for formation errors
Solution Approach 1:
The patent applies preliminary action by forming placeholder structures (stadium structures with trenches) before final conductive material deposition. These placeholders are formed with relaxed precision requirements, then later replaced with precisely positioned conductive contact structures that achieve the required electrical connections without suffering from the same fabrication errors
Solution Approach 2:
The patent uses intermediary placeholder structures (stadium structures containing trenches) as mediators between the stack structure and final conductive contacts. These intermediaries simplify the fabrication process while enabling precise final positioning of conductive materials through subsequent selective removal and refilling operations
2Productivity
If feature packing density is increased to improve memory device density, then productivity is improved, but manufacturing precision deteriorates due to reduced margins for formation errors
Solution Approach 1:
The methodology performs preliminary formation of stadium structures and trenches with relaxed precision tolerances, then uses subsequent processing steps (selective removal, conductive material deposition) to achieve the final high-precision electrical connections. This decouples the density-enabling structure formation from the precision-critical contact formation
Solution Approach 2:
The patent segments the fabrication process into distinct stages: forming placeholder stadium structures, creating trenches within them, selectively removing portions, and depositing conductive materials. This segmentation allows each stage to be optimized independently, with earlier stages focused on density and later stages on precision
Data Source
AI summary
A microelectronic device having a stack structure with an alternating sequence of conductive material and insulative material arranged in tiers, and having blocks separated by dielectric slot structures. Each of the blocks has a stadium structure, a filled trench overlying the stadium structure, support structures extending through the filled trench and tiers of the stack structure, and dielectric liner structures covering sidewalls of the support structures. The stadium structure has staircase structures each having steps with edges of the tiers of the stack structure. The filled trench has a dielectric material interposed between at least two additional dielectric materials. The dielectric liner structures have first protrusions at vertical positions of the dielectric material, and second protrusions at vertical positions of the conductive material of the tiers of the stack structure. The second protrusions have greater horizontal dimensions that the first protrusions. Memory devices, electronic systems, and methods are also described.