3D Memory Stack Insulation for Staircase Stress Stability
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Solution Overview
Problem
The challenge in increasing the integration density of semiconductor devices is limited by the expensive equipment required for fine pattern formation in two-dimensional devices, leading to the exploration of three-dimensional semiconductor devices, where structural stability and fabrication process reliability are critical.
Innovation Solution
A semiconductor device design featuring a substrate with a cell array and connection region, including vertically stacked electrodes with a staircase structure, a planarization insulating layer composed of high-density plasma oxide and tetraethyl orthosilicate oxide, and penetration plugs to enhance structural stability and reduce fabrication failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional or planar semiconductor devices are used, then fine pattern formation can be achieved, but expensive process equipment is required which sets a practical limitation on increasing integration
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked devices. By stacking multiple active regions and interconnect structures vertically, the device achieves higher integration density without requiring further reduction in pattern size, thus avoiding the need for expensive fine pattern formation equipment while maintaining manufacturing feasibility.
2Productivity
If three-dimensional semiconductor devices with vertically stacked structures are implemented, then integration density is improved, but structural stability becomes critical and fabrication failures increase
Solution Approach 1:
The patent introduces stressor structures and compensation structures during the fabrication process to preemptively counteract stress-induced defects. These structures are designed to compensate for stress accumulation before it causes fabrication failures, thereby maintaining high integration density while improving fabrication reliability.
Solution Approach 2:
The patent modifies material parameters by introducing stressor structures with specific stress characteristics and compensation structures with tailored mechanical properties. By changing the stress state parameters within the vertically stacked structure, the device maintains structural stability and reduces fabrication failures while preserving high integration density.
3Productivity
If vertically stacked electrodes with staircase structure are used, then integration density increases, but stress and interfacial defects may cause structural instability
Solution Approach 1:
The patent introduces compensation structures as intermediary elements between the vertically stacked electrodes and the substrate. These compensation structures act as mediators that redistribute and alleviate stress concentrations at critical interfaces, preventing structural instability while maintaining the high integration density enabled by the staircase structure.
Solution Approach 2:
The patent employs composite structures combining different materials with complementary mechanical properties. The stressor and compensation structures are formed from materials selected to provide appropriate stress characteristics and mechanical support, creating a composite system that maintains structural stability in the vertically stacked configuration.
Data Source
AI summary
A semiconductor device may include a substrate including a cell array region and a connection region, a stack including electrodes, which are vertically stacked on the substrate, and which have a staircase structure in the connection region, channel regions provided on the cell array region that vertically extend through the stack, and a planarization insulating layer that covers the stack in the connection region. The planarization insulating layer may include a first insulating layer in contact with the stack and a second insulating layer that covers the first insulating layer. The first insulating layer may include high-density plasma (HDP) oxide, which is doped with first dopants, and the second insulating layer may include tetraethyl orthosilicate (TEOS) oxide, which is doped with second dopants.