3D Memory Cell Stack Layout Without Staircase Wiring
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor structures face challenges in maximizing integration level and spatial utilization due to the limitations of memory cell stacking and wasted space in staircases, which hinder further improvements in performance and efficiency.
Innovation Solution
The semiconductor structure incorporates at least two leading wire posts that directly contact different layers of memory cells, eliminating the need for a separate staircase, thereby improving spatial utilization and integration level by reducing the number of stairs and optimizing the arrangement of memory cells and wire connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate staircases are arranged for leading wire posts to contact different layers of memory cells, then electrical connection between layers is achieved, but significant area is occupied and spatial utilization is hindered
Solution Approach 1:
The patent merges the leading wire posts with the memory cell stack structure by having the wire posts extend through multiple memory cell groups and contact memory cells at different layers directly, eliminating the need for separate staircase structures. This integration reduces the occupied area while maintaining electrical connection functionality.
Solution Approach 2:
The patent transitions from a planar staircase arrangement to a vertical three-dimensional arrangement where leading wire posts extend through the height of multiple memory cell layers. This dimensional change allows electrical connections to be made directly through the stack without requiring lateral staircase extensions, thereby reducing the area occupied.
2Quantity of substance
If multiple stacked layers of memory cells are added to increase integration level, then the number of memory cells increases, but the number of required staircases and wire posts increases accordingly, occupying more area
Solution Approach 1:
The leading wire posts serve multiple functions simultaneously: they provide electrical connections to memory cells at different layers, act as structural support elements, and extend through multiple memory cell groups. This multi-functionality reduces the need for separate staircase structures for each layer, thereby reducing the area occupied by support structures while maintaining the ability to access multiple memory cell layers.
3Quantity of substance
If the volume of memory cells is reduced to increase integration level, then more memory cells can be accommodated, but the volume reaches a scaling limit under physical property constraints
Solution Approach 1:
The patent transitions from a planar two-dimensional memory cell arrangement to a three-dimensional stacked structure where memory cells are arranged in multiple layers vertically. This allows more memory cells to be accommodated by utilizing the vertical dimension rather than continuously reducing the volume of individual cells, thereby overcoming the scaling limit imposed by physical property constraints.
4Quantity of substance
If the number of stacked layers of memory cells is increased to improve integration level, then more memory cells can be accommodated, but it is difficult to increase the number of layers under process factor limits
Solution Approach 1:
The patent divides the memory structure into multiple memory cell groups, each containing stacked memory cells. The leading wire posts extend through these segmented groups and contact memory cells at different layers. This segmentation approach allows the structure to be built in manageable units while achieving a high total number of layers and memory cells, thereby reducing the complexity associated with manufacturing very high-layer stacks.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The embodiments of the disclosure relate to the field of semiconductors and provide a semiconductor structure and a method for manufacturing the semiconductor structure, a memory chip and an electronic device. The semiconductor structure comprises a substrate on which a stacked structure is provided, the stacked structure comprising a plurality of memory cell groups arranged in a first direction, each of the memory cell groups comprising multiple layers of memory cells arranged in a second direction; and a plurality of leading wire posts, wherein at least two leading wire posts are respectively in contact with the memory cells of different layers in different memory cell groups. The embodiments of the disclosure can at least improve an integration level of the semiconductor structure.