Memory Die Stack Standby Exit for High-Speed Bus Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Maintaining high throughput and maximizing interface speeds in stacked memory devices is challenging due to internal connection delays, CMOS process skew, and capacitive loading effects that interfere with signal transmission on shared buses.
Innovation Solution
A stacked memory device with an intra-package bus that couples a primary die to multiple secondary dies, using an intra-package communication protocol that enables high concurrency with reduced capacitive loading, and employing opcode-based standby command structures to improve manufacturing efficiency and device flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory dies are stacked to increase density, then memory capacity is improved, but internal connection delays and timing synchronization become problematic
Solution Approach 1:
The patent divides the memory system into multiple independent dies (first die, second die, third die) that can be individually addressed and activated. Each die has its own command interface and can operate independently, allowing the system to access only the necessary die rather than all dies simultaneously, thereby reducing timing delays.
Solution Approach 2:
The patent introduces a command interface and control logic that acts as an intermediary between the host and multiple memory dies. This intermediary manages the complex timing and coordination required for multi-die operations, handling address routing and command scheduling to minimize synchronization delays.
2Device complexity
If multiple memory dies share a common bus, then device complexity is reduced, but capacitive loading effects increase and interfere with signal transmission
Solution Approach 1:
The patent segments the bus interface into multiple dedicated interfaces, with each memory die having its own command interface. This segmentation isolates the capacitive loading of each die from the others, preventing cumulative loading effects while maintaining a relatively simple overall architecture.
Solution Approach 2:
The patent transitions from a shared single-dimension bus to a multi-dimensional interface structure where each die has its own interface pathway. This dimensional change allows independent signal transmission to each die, eliminating the capacitive loading problem of shared buses while avoiding excessive complexity.
3Productivity
If all memory dies remain active to maintain high throughput, then data access speed is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management where memory dies can transition between active and standby states based on access patterns. The system activates only the necessary die for current operations while placing others in low-power standby mode, dynamically adjusting power consumption to match actual throughput requirements.
Solution Approach 2:
The patent employs periodic activation of memory dies based on access patterns and data locality. Instead of keeping all dies continuously active, the system periodically activates specific dies when their data is needed, creating a rhythm of activity that maintains throughput while reducing average power consumption during idle periods.
Data Source
AI summary
A memory device standby procedure can include idling a first memory device in a low-power standby mode, the first memory device coupled to a memory interface that couples multiple memory devices to a host and includes a command line (CA) and a standby exit line (EX), and the first memory device can include a primary die coupled to multiple secondary dies using an intra-package bus. At the first memory device, the procedure can include waking receiver circuitry on the primary die in response to a state change on the standby exit line, and sampling the command line using logic circuitry on the primary die. When a wakeup message on the command line comprises a chip identification that corresponds to the first memory device, the procedure can include initiating a standby exit procedure for the first memory device.