3D Memory Stack Stepped Grooves for Stable High-Density Etching
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Solution Overview
Problem
The integration of two-dimensional semiconductor memory devices is limited due to the high cost of equipment required for miniaturizing fine patterns, necessitating the development of three-dimensional semiconductor memory devices.
Innovation Solution
A semiconductor memory device with a stack of conductive layers and interlayer insulating layers alternately stacked on a substrate, featuring stepped grooves at different depths and openings connected to these grooves, allowing for vertical penetration and structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices are used, then manufacturing equipment cost is high, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional stacked memory structures. Multiple memory layers are vertically stacked on a single substrate, with each layer containing memory cells formed by intersecting word lines and bit lines. This vertical stacking enables significantly higher integration density without requiring additional substrate area, thereby avoiding the need for expensive miniaturization equipment while achieving increased capacity.
2Manufacturing precision
If complex etching processes are used to form patterns, then manufacturing precision is improved, but pattern collapse occurs
Solution Approach 1:
The etching process is divided into multiple sequential steps, each forming patterns at different depths. First, shallow grooves are etched to a certain depth, then deeper grooves are etched in subsequent steps. This segmentation allows each etching step to work on a manageable depth range, maintaining pattern stability and preventing collapse while achieving the required manufacturing precision for three-dimensional structures.
Solution Approach 2:
Shallow grooves are formed in advance before forming deeper grooves. These preliminary shallow grooves serve as guides and support structures for subsequent deeper etching steps, preventing pattern collapse during the etching process while enabling precise formation of the final three-dimensional pattern structure.
3Quantity of substance
If more process steps are added to form three-dimensional structures, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The stacked memory structure uses identical or similar process steps repeated across multiple layers. Word lines, bit lines, and memory cells in different layers are formed using the same etching, deposition, and patterning techniques. This multi-functionality of process steps reduces manufacturing complexity despite increased integration density, as the same equipment and methods can be applied iteratively to create each additional memory layer.
Solution Approach 2:
Multiple memory layers are nested vertically within a single substrate structure. Each memory layer is contained within the three-dimensional stack, with lower layers serving as foundations for upper layers. This nesting approach achieves high integration density without proportionally increasing manufacturing complexity, as the overall structure is built systematically layer by layer using consistent process flows.
Data Source
AI summary
A semiconductor memory device includes a stack including a plurality of conductive layers and a plurality of first interlayer insulating layers which are alternately stacked on a first substrate; a plurality of stepped grooves defined at different depths in the stack; and an opening vertically passing through the stack and formed integrally with one of the plurality of stepped grooves, wherein the opening includes a step on a sidewall, and wherein the step has a height the same as a difference in depth between two stepped grooves of the plurality of stepped grooves.