3D Memory Stack Bonding Layout for High Integration and Stress Balance
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Solution Overview
Problem
Current memory devices face challenges in achieving high integration and reduced planar area while maintaining efficient connectivity and stress balance, which affects their performance and reliability.
Innovation Solution
The memory device is designed with two structures coupled together, featuring a first structure with a peripheral circuit and a second structure with a memory cell array, where conductive patterns are recessed into the substrate to reduce height and stress, and the substrate wiring structure connects components, allowing for flexible design and reduced warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory devices are highly integrated with increased degree of integration, then performance and capacity improve, but planar area and device complexity increase
Solution Approach 1:
The patent transitions from planar 2D layout to 3D vertical stacking by forming memory holes and channel structures that extend through multiple insulating layers. Word lines, bit lines, and select lines are arranged in vertical stacks, enabling high integration without increasing planar footprint.
Solution Approach 2:
Multiple functional layers are nested within each other vertically: insulating layers contain conductive patterns, which contain channel structures, which are surrounded by gate structures. This nested arrangement packs maximum functionality into minimal planar space.
2Area of stationary object
If conductive patterns are recessed into substrate to reduce height, then planar area and stress balance improve, but manufacturing complexity increases
Solution Approach 1:
The conductive patterns are divided into multiple segments: some remain on the substrate surface while others are recessed into the substrate at different depths. This segmentation allows optimization of each region's function and stress distribution.
Solution Approach 2:
Different regions of the conductive patterns have different properties: surface patterns provide electrical connectivity while recessed patterns reduce height and balance stress. The insulating layers are also selectively positioned to provide local stress management and electrical isolation.
3Ease of operation
If bonding pads are positioned to connect peripheral circuit to memory cell array, then connectivity and functionality improve, but device complexity and area increase
Solution Approach 1:
The bonding pads serve multiple functions: they provide electrical connectivity between peripheral circuits and memory cell arrays, act as stress distribution elements, and enable modular device assembly. This multi-functionality reduces the need for separate dedicated structures.
Data Source
AI summary
A memory device including a first structure; and a second structure on the first structure, wherein the first structure includes a first substrate; a peripheral circuit on the first substrate; a first insulating layer covering the first substrate and the peripheral circuit; and a first bonding pad on the first insulating layer, the second structure includes a second substrate; a memory cell array on a first surface of the second substrate; a second insulating layer covering the first surface of the second substrate and the memory cell array; a conductive pattern at least partially recessed from a second surface of the second substrate; and a second bonding pad on the second insulating layer, the first bonding pad is in contact with the second bonding pad, and the conductive pattern is spaced apart from the second insulating layer.