Memory Device Stack Film Stress Control
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Solution Overview
Problem
Semiconductor memory devices face issues with wafer bowing and litho overlay shifts due to compressive stress from tantalum nitride layers, which can lead to buckling defects and undesirable columnar film morphology in titanium nitride electrodes.
Innovation Solution
A semiconductor structure is developed with a combination of compressive and tensile metal-containing layers, where a compressive metal-containing layer is in direct contact with a memory device pillar, and a tensile metal-containing layer is applied on top to compensate for the compressive stress, reducing wafer bowing and litho overlay shifts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If tantalum nitride is deposited by PVD to provide compressive stress, then wafer bowing and litho overlay issues are minimized, but buckling defects occur and structural integrity deteriorates
Solution Approach 1:
The patent uses a composite metal-containing layer structure combining multiple materials (e.g., tungsten, molybdenum, copper, or aluminum) to achieve both compressive stress control and structural integrity. This composite approach allows optimization of stress properties without the buckling defects associated with pure tantalum nitride PVD layers.
Solution Approach 2:
The patent modifies stress parameters by controlling the composition, thickness, and deposition conditions of metal-containing layers. By adjusting these parameters, the system achieves neutral or balanced stress states that prevent both excessive bowing and buckling, resolving the contradiction between manufacturing precision and structural reliability.
2Stress or pressure
If titanium nitride is deposited by PVD to provide tensile stress, then compressive stress is compensated, but columnar film morphology is formed which provides diffusion paths
Solution Approach 1:
The patent changes the deposition parameters and material composition to achieve the desired tensile stress without forming columnar morphology. By controlling nitrogen content, deposition temperature, and layer thickness, the system obtains a dense film structure that provides both stress compensation and diffusion barrier properties.
Solution Approach 2:
The patent employs composite metal-containing layers that combine materials with different properties to achieve both tensile stress and dense film morphology. This composite structure prevents diffusion paths while maintaining the necessary stress characteristics to counterbalance compressive stress from other layers.
3Reliability
If thick conducting metal layers are used for bottom and top electrodes, then electrical conductivity is improved, but wafer bowing and buckling defects increase
Solution Approach 1:
The patent uses composite metal-containing layers with optimized composition and thickness to achieve the necessary electrical conductivity while controlling stress. By combining materials with different mechanical and electrical properties, the system maintains high conductivity without excessive thickness that would cause bowing or buckling.
Solution Approach 2:
The patent applies different material compositions and thicknesses to different regions or functions within the electrode structure. This local optimization allows thick enough layers for conductivity in critical areas while using thinner or stress-compensated layers in areas where bowing is a concern, achieving both electrical performance and wafer flatness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively minimizes wafer bowing and litho overlay issues by achieving neutral stress, improving the structural integrity and patterning accuracy of the semiconductor memory devices.
Implementation Method 1
a tensile metal-containing layer is formed above the memory device stack, wherein the tensile metal-containing layer compensates the compressive stress caused by the compressive metal-containing layer
Data Source
AI summary
Semiconductor structures are provided that include a memory device buried within interconnect dielectric materials and in which a combination of a compressive metal-containing layer and a tensile metal-containing layer have been used to minimize wafer bow and litho overlay shift as well as a method of forming such semiconductor structures.