3D Memory Stack Layout to Limit Stress-Induced Deformation
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Solution Overview
Problem
In semiconductor memory devices with a three-dimensional structure, the mixing of insulating and conductive layers can lead to stress-induced deformation due to material differences, particularly in the memory cell region where through contacts penetrate insulating portions.
Innovation Solution
The semiconductor memory device incorporates a stacked body with alternately stacked conductive and insulating layers, and includes first plate-like portions that penetrate the stacked body, creating a gap between them. This configuration allows for the formation of a staircase region with conductive layers as step surfaces, reducing stress and deformation by maintaining the integrity of the stacked body.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If through contacts are provided to penetrate insulating portions in the memory cell region, then the peripheral circuit can be connected to wirings above the memory cell region, but the insulating portion and the stacked body may be deformed by stress due to material difference
Solution Approach 1:
The patent divides the memory cell region into multiple regions by introducing plate-like portions that extend in the first direction. These plate-like portions segment the region into a first region with the stacked body and a second region with the insulating portion, preventing stress mixing while maintaining electrical connectivity through the through contacts.
Solution Approach 2:
The patent applies different structural configurations to different regions: the first region contains the stacked body with conductive and insulating layers for memory cell formation, while the second region contains the insulating portion for through contact formation. This local differentiation allows each region to maintain its structural integrity while fulfilling its specific function.
2Speed
If the staircase shape is provided at the center portion of the memory cell region, then the resistance of the word line is lowered and operation speed is improved, but the insulating portion and stacked body mixing increases stress deformation
Solution Approach 1:
The patent segments the memory cell region using plate-like portions that create distinct areas for the stacked body and insulating portion. This segmentation allows the staircase shape to be formed at the center for improved word line resistance and speed, while preventing stress deformation by isolating the insulating portion from the stacked body.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes: a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one; and a plurality of first plate-like portions that penetrate the stacked body in a stacking direction thereof and cross the stacked body in a first direction intersecting the stacking direction, the plurality of first plate-like portions being arranged along the first direction with a gap therebetween.