3D Memory Stack Trench Buffering for Over-Verify Prevention
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Solution Overview
Problem
As semiconductor devices are scaled down, they face challenges such as short channel effects, leading to degradation of operation characteristics and increased power consumption, necessitating methods for improved reliability and lower power consumption in smaller form factors.
Innovation Solution
A method of manufacturing semiconductor devices involves forming a preliminary source structure, a stack structure with alternating material layers, creating trenches, performing surface treatments to form buffer patterns, and applying protective layers to enhance integration and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of semiconductor devices is reduced to increase integration, then the integration density is improved, but short channel effects occur leading to degradation of operation characteristics
Solution Approach 1:
The device is segmented into multiple functional layers including alternating insulating layers and sacrificial layers stacked vertically. This segmentation allows each layer to perform specific functions while maintaining overall device performance despite size reduction
Solution Approach 2:
The patent transitions from planar device architecture to three-dimensional vertical stacking. Multiple layers are stacked in the vertical dimension to achieve higher integration density while maintaining adequate channel length to avoid short channel effects
2Productivity
If the size of semiconductor devices is reduced to increase integration, then the integration density is improved, but power consumption increases
Solution Approach 1:
The device structure is divided into multiple functional layers with insulating and sacrificial layers alternating vertically. This segmentation enables better electrical isolation and controlled current flow paths, reducing leakage and power consumption in highly integrated devices
Solution Approach 2:
By stacking layers vertically in the third dimension, the patent achieves high integration density without proportionally increasing power consumption. The vertical architecture allows for optimized current paths and reduced parasitic effects compared to lateral scaling
3Reliability
If surface treatment is performed on exposed portions to form buffer patterns, then reliability is improved by preventing over verify failures, but manufacturing complexity increases
Solution Approach 1:
Surface treatment is performed on exposed portions of the sacrificial layers before final device completion. This preliminary action forms buffer patterns that prevent over verify failures in subsequent processing steps, addressing reliability issues before they manifest
Solution Approach 2:
The buffer patterns formed by surface treatment act as intermediary structures between the sacrificial layers and subsequent processing steps. These intermediate buffer patterns control material deposition and etching processes, preventing over verify failures while maintaining manufacturability
Data Source
AI summary
The present technology provides a method of manufacturing a semiconductor device. The method includes forming a preliminary source structure, forming a stack structure on the preliminary source structure, the stack structure including a first material layer and a second material layer, forming a preliminary memory layer that penetrates the stack structure, forming a trench passing through the stack structure, forming a first buffer pattern by performing a surface treatment on a portion of the second material layer that is exposed by the trench, and forming a protective layer covering the first buffer pattern.