3D Memory Stack Layout With Tungsten Word Line Replacement
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently manufacturing stacked structures for select gate lines and word lines, which results in increased complexity and size due to the need for support structures and multiple slits.
Innovation Solution
The semiconductor memory device employs a method where silicon oxide and polysilicon are alternately stacked to form layers, and polysilicon within memory holes is replaced with tungsten, reducing the number of slits and support members, thereby simplifying the structure and reducing size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional manufacturing methods are used for stacked structures of select gate lines and word lines, then the structure provides sufficient support and electrical connectivity, but the device size increases and manufacturing complexity increases due to required support structures and multiple slits
Solution Approach 1:
The patent merges the functions of support structures and conductive layers by integrating polysilicon layers that serve dual purposes: providing mechanical support to the stacked structure and serving as conductive pathways. This eliminates the need for separate support structures, reducing manufacturing steps and structural complexity while maintaining both mechanical integrity and electrical connectivity.
Solution Approach 2:
The polysilicon layers are designed to perform multiple functions simultaneously: they provide structural support to maintain the stacked configuration, act as conductive layers for electrical connectivity, and serve as spacers to maintain dimensional relationships between layers. This multi-functionality reduces the overall component count and simplifies the manufacturing process.
2Reliability
If support structures and multiple slits are used in the stacked structure, then mechanical stability and electrical connectivity are ensured, but the device area increases
Solution Approach 1:
The patent employs thin polysilicon films that provide sufficient mechanical support and electrical conductivity without requiring thick support structures. These thin films maintain the structural integrity of the stacked configuration while occupying minimal space, thereby reducing the overall device area while preserving reliability.
Solution Approach 2:
The patent transitions from a planar layout requiring multiple slits and support structures to a vertically stacked three-dimensional configuration. By stacking conductive layers and insulating films in the vertical dimension, the design achieves the necessary structural stability and electrical connectivity without increasing the horizontal device area, effectively moving functionality from two dimensions to three dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of slits and support members, shortening the distance between tungsten layers and allowing for a more compact and efficient semiconductor memory device design.
Implementation Method 1
polysilicon within memory holes is replaced with tungsten
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a plurality of first conductive layers that each include tungsten; a plurality of insulating films that include a stacked portion and a first projecting portion projecting; a semiconductor layer extending through an inside of a stacked body; a charge storage layer arranged between the plurality of first conductive layers and the semiconductor layer; a plurality of second conductive layers that are each arranged on the first projecting portion in such a manner as to be in contact with a single first conductive layer and that include silicon containing an impurity; and a plurality of contact plugs that are each provided on a single second conductive layer in such a manner as to be in contact with the single second conductive layer.