3D Memory Cell Stack Formation for Select-Gate Via Alignment
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Solution Overview
Problem
Existing memory technologies face challenges in efficiently forming vertically-stacked memory cells with precise control over the distance between select-gate channel material and via connections, leading to potential electrical coupling issues and reduced performance.
Innovation Solution
A method involving the formation of vertically-alternating tiers with selective etching and simultaneous deposition of materials to create memory cell structures, including channel material, storage material, and charge-passage material, followed by the formation of select gates and conductive vias for precise electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional memory cell formation methods are used, then manufacturing simplicity is maintained, but manufacturing precision of the distance between select-gate channel material and via connections deteriorates
Solution Approach 1:
The patent applies preliminary action by forming placeholder structures (such as sacrificial layers or temporary fill materials) during the fabrication process to pre-establish the correct spatial relationships and distances between select-gate channel material and via connections. These placeholders are removed or transformed in subsequent steps, having already ensured the precise positioning is achieved before final component formation.
Solution Approach 2:
The patent uses intermediary elements such as sacrificial layers, placeholder structures, or temporary materials that mediate the positioning process. These intermediaries are introduced to control the distance and alignment between components during fabrication, then removed or transformed after serving their positioning function, thereby achieving precise spatial control without requiring direct measurement and adjustment.
2Reliability
If precise control of electrical connections is implemented, then reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent ensures reliable electrical coupling by preliminarily establishing correct alignments and connections through placeholder structures and controlled deposition processes. The spatial relationships are predetermined and fixed during fabrication using intermediary elements, ensuring that when final components are formed, the electrical connections are already optimally positioned for reliable operation.
Solution Approach 2:
Intermediary structures such as sacrificial layers and placeholder materials serve as mediators to achieve precise electrical coupling. These intermediaries enable controlled formation of conductive paths and connections during fabrication, then are removed or transformed after ensuring reliable electrical connectivity between components.
3Quantity of substance
If vertically-stacked memory cell structures are formed, then storage density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs intermediary placeholder structures and sacrificial layers to mediate the formation of vertically-stacked memory cells. These intermediaries establish precise alignment and spacing between stacked components during fabrication, enabling high-density vertical integration while maintaining manufacturing feasibility through controlled, step-by-step assembly with built-in positioning features.
Data Source
AI summary
A method used in forming memory circuitry comprises forming a stack where strings of memory cells will be formed and a select-gate region directly above the stack. The stack comprises vertically-alternating different-composition first tiers and second tiers having lower channel openings extending there-through. The select-gate region comprises upper channel openings extending there-through and that are individually directly above and extend to individual of the lower channel openings. Storage material of the strings of memory cells is formed simultaneously in the upper and lower channel openings. Then, insulative charge-passage material of the strings of memory cells is formed simultaneously in the upper and lower channel openings. Then, channel material is formed simultaneously in the upper and lower channel openings. The storage material is removed from the upper channel openings. After the removing, a select gate is formed in the select-gate region operatively aside the channel material in the select-gate region. Other embodiments, including structure, are disclosed.